tirumalnaidu
Graduate Student at University of Wisconsin-Madison | Computer Architecture & Systems
University of Wisconsin-MadisonMadison, United States
Pinned Repositories
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
buffets
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
csi-nn2
An optimized neural network operator library for chips base on Xuantie CPU.
opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
Oximetry-FFT
SpO2 and Heart Beat Measurement of PPG Data using Fast Fourier Transform
pipelined-mips-uvm
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
scenic-accelerator
DNN Accelerator for Medical Applications
uvm-i2c-controller
UVM Verification of i2c Master Core Wishbone Specification
WISC_F24_RISC_Processor
WISC-F24 ISA Based Processor Implementation (ECE 552 Course Project)
tirumalnaidu's Repositories
tirumalnaidu/opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
tirumalnaidu/Oximetry-FFT
SpO2 and Heart Beat Measurement of PPG Data using Fast Fourier Transform
tirumalnaidu/uvm-i2c-controller
UVM Verification of i2c Master Core Wishbone Specification
tirumalnaidu/pipelined-mips-uvm
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
tirumalnaidu/scenic-accelerator
DNN Accelerator for Medical Applications
tirumalnaidu/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
tirumalnaidu/csi-nn2
An optimized neural network operator library for chips base on Xuantie CPU.
tirumalnaidu/devoloper_manual
tirumalnaidu/DPU-TRD-ZCU104
tirumalnaidu/FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
tirumalnaidu/WISC_F24_RISC_Processor
WISC-F24 ISA Based Processor Implementation (ECE 552 Course Project)
tirumalnaidu/gemmini
Berkeley's Systolic Array Generator
tirumalnaidu/Hadware_Convolutional-Module
Hardware implementation of a configurable Convolutional Module.
tirumalnaidu/hardware-multiplier-architectures
Verilog implementations of 6 different hardware multiplier architectures
tirumalnaidu/MAERI_bsv
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
tirumalnaidu/nncase
Open deep learning compiler stack for Kendryte K210 AI accelerator
tirumalnaidu/nvdla-sw-new
tirumalnaidu/onnc-tutorial
tirumalnaidu/open-gpu-kernel-modules
NVIDIA Linux open GPU kernel module source
tirumalnaidu/openc910
OpenXuantie - OpenC910 Core
tirumalnaidu/processor
tirumalnaidu/rachitnigam.com
Rachit Nigam's personal website.
tirumalnaidu/RayTracing-OSHW
A dedicated graphical processor for ray tracing
tirumalnaidu/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
tirumalnaidu/ThePBone
tirumalnaidu/tirumalnaidu
tirumalnaidu/tpu-mlir
Machine learning compiler based on MLIR for Sophgo TPU.
tirumalnaidu/tvm_mlir_learn
tvm learn
tirumalnaidu/vortex
tirumalnaidu/wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware