Pinned Repositories
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
awesome-ISP
A curated list of awesome ISP frameworks, papers, libraries, resources, and shiny things.
chisel-book
Digital Design with Chisel
darkriscv
opensouce RISC-V implemented from scratch in one night!
e200_opensource
The Ultra-Low Power RISC Core
gen_apb_file
mips-cpu
MIPS CPU implemented in Verilog
NyuziProcessor
GPGPU microprocessor architecture
Open_RegModel
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
tjupathfinder's Repositories
tjupathfinder/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
tjupathfinder/awesome-ISP
A curated list of awesome ISP frameworks, papers, libraries, resources, and shiny things.
tjupathfinder/chisel-book
Digital Design with Chisel
tjupathfinder/darkriscv
opensouce RISC-V implemented from scratch in one night!
tjupathfinder/e200_opensource
The Ultra-Low Power RISC Core
tjupathfinder/gen_apb_file
tjupathfinder/mips-cpu
MIPS CPU implemented in Verilog
tjupathfinder/NyuziProcessor
GPGPU microprocessor architecture
tjupathfinder/Open_RegModel
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
tjupathfinder/OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
tjupathfinder/riscv
RISC-V CPU Core (RV32IM)
tjupathfinder/riscv-elf-psabi-doc
A RISC-V ELF psABI Document
tjupathfinder/SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.0 CoreMark/MHz.
tjupathfinder/systemctlm-cosim-demo
tjupathfinder/YASA
:snail:Yet Another Simulation Architecture