/ScoreBoard-wTimer

Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.

Primary LanguageVerilogGNU General Public License v3.0GPL-3.0

Score-Board-FPGA-Verilog:

GitHub Workflow Status (with branch) Libraries.io dependency status for GitHub repo GitHub release (latest SemVer) GitHub

Demo Video Link

Meet the team:

This project was completed in EGCP 446 Fall 2022 by Duy, Jeremy and Spencer. Spencer contributed the module used to keep team scores, I contributed by creating the countdown timer. Lastly, Duy setup the 7 segment!

Initial setup:

Install Xilinx Vivado

Download zip folder:

Open vivado and import project to IDE

Connect FPGA board:

Make sure to select correct FPGA board, Nexy's A7

Create Bitstream:

Once created you can then load program unto board and test software running.

Screen shot of FPGA board:

Screen Shot 2023-01-18 at 2 34 40 PM

License info:

Copyright ©2023 Duy, Jeremy and Spencer -> MIT License