WE WILL MAKE ALL ANNOUNCEMENTS VIA PIAZZA, SO MAKE SURE THAT YOU ENROLL
If neither this site nor the Piazza has the information you need, you should email the TA's directly
2021
February March April May
Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa
1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1
7 8 9 10 11 12 13 7 8 9 10 11 12 13 4 5 6 7 8 9 10 2 3 4 5 6 7 8
14 15 16 17 18 19 20 14 15 16 17 18 19 20 11 12 13 14 15 16 17 9 10 11 12 13 14 15
21 22 23 24 25 26 27 21 22 23 24 25 26 27 18 19 20 21 22 23 24 16 17 18 19 20 ...
28 28 29 30 31 25 26 27 28 29 30
!!! Note: This schedule is tentative and may change throughout the semester. !!!
L: parsing~55
means that the topic was parsing
and we covered up to slide 55
.
Monday | Tuesday | Wednesday | Thursday | Friday | |
---|---|---|---|---|---|
02/15 - 02/19 |
FIRST DAY LOGISTICS FORM L: regex~39 |
L: regex~62 | L: top-down~53 | P1 RELEASE L: top-down~$ |
|
02/22 - 02/26 |
P1 OH (during lecture slot) |
||||
03/01 - 03/05 |
L: shift-reduce~104 | L: shift-reduce~133 | L: shift-reduce~$ L: IR~52 |
L: IR~$ | P1 DUE P2 RELEASE PSET A L: sem~$ |
03/08 - 03/12 |
Student holiday | SUBMIT TEAM L: codegen~58 |
L: codegen~79 | L: codegen~$ | |
03/15 - 03/19 |
ADD DATE P2 DUE |
||||
03/22 - 03/26 |
Student holiday | Student holiday | L: dataflow~31 | L: dataflow | PSET A DUE L: dataflow |
03/29 - 04/02 |
L: dataflow | L: dataflow | L: dataflow | L: dataflow | L: dataflow |
04/05 - 04/09 |
P3 DUE | ||||
04/12 - 04/16 |
L: loops | L: loops | L: reg | CPW L: lattice |
CPW L: lattice |
04/19 - 04/23 |
Patriots' Day | Student holiday | L: lattice | L: lattice | P4 DUE L: lattice |
04/26 - 04/30 |
L: parallel | L: parallel | DROP DATE | PSET B DUE | |
05/03 - 05/07 |
CHECKPOINT | ||||
05/10 - 05/14 |
|||||
05/17 - 05/21 |
P5 DUE | LAST DAY DERBY |
- Faculty
- Martin Rinard rinard@csail.mit.edu
- Michael Carbin mcarbin@csail.mit.edu
- TA
- Mark Theng mtheng@mit.edu
- Prereq --
6.004
,6.031
- Level --
U
- Units --
4-4-4
Analyzes issues associated with the implementation of higher-level programming languages. Fundamental concepts, functions, and structures of compilers. The interaction of theory and practice. Using tools in building software. Includes a multi-person project on compiler design and implementation.
6.035 has no officially required textbook. All of the material you need is taught in class, with the exception of the documentation for your implementation language and associated libraries. However, the following books may be helpful in implementing various components of your compiler, and are available from MIT libraries.
Modern Compiler Implementation in Java (Tiger Book)
Andrew W. Appel and Jens Palsberg
Cambridge University Press, 2002
Many other resources such as technical papers, interesting and useful blog posts, and reference guides are available on the references page.
We will distribute assignments here and make all announcements via Piazza. Important announcements will also be made via email.
Since lecture dates are not all finalized at the start of the semester, please check the schedule regularly.
Component | Weight |
---|---|
Project phases 2 and 3 | 25% |
Project phases 4 and 5 | 50% |
Problem set A | 9% |
Problem set B | 10% |
Miniquizzes | 6% |
For more information on the way the compiler project is graded, see the project overview.
We expect you to submit all components of the class on time. For extensions under extenuating circumstances (e.g., you are sick for a week, family emergencies), we require a letter from one of the student deans at S^3.
Although you may discuss the projects with anybody, you must develop the code yourself. For the scanner/parser project, you must develop your code alone. On all subsequent projects, you should work with your team members, but you may not develop or share any code with other teams.
You may collaborate on the mini-quizzes and the problem sets, but you should write all solutions yourself.
Do not post your lab or homework solutions on publicly accessible web sites or file spaces; this enables cheating for students in future years.
This class involves a group project, where you will build a compiler almost entirely from scratch. Details about the project can be found here. Specific instructions for each phase of the project will be released later in the class.
Lectures:
- 11am-12pm MTWRF on Zoom. The link will be distributed on Piazza.
To find out whether there is lecture on a given day, check the calendar above. Lectures will be recorded, so don't worry if you can't make them.
For all general questions and/or concerns, please post on Piazza.
If the matter is private, please email the TA's directly.
Refer to Piazza for the latest updates about office hours. We will have additional office hours before each quiz and each phase of the project.
This section contains a number of useful and/or interesting references selected by the staff. You are not expected to know most of the material on this page for the class; however, you may find it interesting and helpful.
- The complete Intel x64 manual
- Intel x64 Optimization Reference Manual
- x64 wiki
- x64 cheat sheet -- lists and tables detailing registers and assembly commands
- x86-64 architecture guide -- a walkthrough with an example, and common commands
- Intel x64 manual
- Intel developer manual -- detailed description of some assembly instructions
- x64 cheat sheet -- lists and tables detailing registers and assembly commands
Interesting blog posts, papers, etc
- Overviews
- Blogs
- Russ Cox's Blog -- Russ is one of the developers of Google Go, a pretty interesting language.
- Ian Wienand's Blog -- Whoever he is, he writes about compiler and language internals, the magic black box that is the linker, and more
- Matt Might's Blog -- Matt is a professor at the University of Utah and has written some very interesting articles (e.g. "Yacc is dead")
- Papers
- Register Allocation & Spilling via Graph Coloring -- G.J. Chaitin / 1982. Great (short) paper on simple register allocation.
- Linear Scan Register Allocation
- Iterated Register Coalescing -- Lal George / 1996. Presents improvements/alternative to Chaitin's design. If Chaitin-style (+/-Briggs) register allocation isn't enough for you, this paper is a good read - actually, it's a good read anyway, to understand the tradeoffs
- Superword Level Parallelism combined with loop unrolling, a simple way to implement a vectorizing compiler
- Miscellaneous
- Scala Patterns for Compiler Design
6.823 Advanced Computer Architecture
lecture notes