bcd-to-7-segment

There are 3 repositories under bcd-to-7-segment topic.

Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Language:Verilog3 1 22
henryhale/7-segment-display-decoder
📟 A BCD to seven segment display decoder implementation
Language:JavaScript0 1 01
ATOMIC09/Ten_bit_binary_to_3_digit_7_segment
What happens if I push Quartus Prime to GitHub?
Language:VHDL1 0