Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
VerilogMIT
Issues
- 3
Update README.md of Barrel Shifter
#1 opened by Vedant-02 - 5
Update README.md of Priority encoder
#2 opened by Vedant-02