full-adder
There are 44 repositories under full-adder topic.
nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Elidevin/nandgame.com-solutions
Solutions for NandGame.com
luckykadam/adder
Binary Adder using RNN in Keras
bespoyasov/binary-full-adder-in-the-game-of-life
Binary adder implementation in the Game of Life written in JavaScript using canvas.
Keerthiraj-Nagaraj/IBM-quantum-challenge-2020
My solutions to 5 exercises of IBM quantum challenge 2020. Topics include quantum full-adder circuit implementation, circuit optimization and solving various puzzles using Grover's search algorithm.
MohammadNiknam17/Signed-4BIT-Binary-Multiplier_VHDL-FPGA
These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.
Stavros/Multiplier4bit
A 4bit Multiplier in VHDL
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Zannatul-Naim/Digital-System-Design
Digital System Design Lab Codes using Verilog
DatDarkAlpaca/dat-emulation-sandbox
A simulation where I can connect virtual logic gates and build virtual CIs.
MohammadNiknam17/vending_machine_processor
VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.
aliansgp/VHDL_Adders
Different adders code in VHDL and Comparison
ammarmalik17/Verilog_Adders
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
CedricRev/simple-calculator-verilog
An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.
imvickykumar999/Logical-Redstone-Reloaded
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
jamestiotio/DigiAlpha
Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver
jgesc/VerilogTests
A repository for some modules I made while learning Verilog
jhenals/VHDL-Code---Carry-Select-32bit
Progetto di Elettronica Digitale AA 2022-2023
joeymaillette04/VHDL
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
mcquerol/electronic-systems
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
PARSA-MHMDI/design-ALU-with-Xilinx-ISE
This is Amirkabir University Logic Circuit Design final project 2022
rahul21316/verilog-adders
All the various adders in Verilog!
utkarshad21/4-bit-Full-Adder-using-Verilog-HDL
Verilog code and testbench for 4-bit full adder
afzalamu/8Bit-signed-Full-Adder-on-ARTIX-7-FPGA
Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.
akorkos/digital-electronic-systems
Digital Circuits made with VHDL
levyashvin/verilog_codes
basic implementation of logic structures using verilog (revising github)
LiamK-Technion/DigSystems_sim1
Digital Systems and Computer Structure, Simulation 1, Spring 2022
PoulamiSarkar24/VHDL
This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.
archy-co/IC_Testers
Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4
bislerium/decadder
➕A simple python script to add two numbers by converting them to binaries and applying to a aggregated digital logic of Full adders. Uses AND, OR, XOR gates.
gubbriaco/VHDL_scripts
Useful VHDL scripts for hardware description.
JalalSayed1/N-bit-Full-Adder
N-bit Full Adders implementation in VHDL
krish1925/CS-M152A
Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
newajsharif91/Verilog_HDL_Digital-System-Design
CSE-2112 Digital Syatem Design LAb
royb11/QuantumFullAdder
Implementing Full Adder using QISKIT and IBMQ infrastructure for computation