carry-look-ahead-adder
There are 20 repositories under carry-look-ahead-adder topic.
hoangsonww/Digital-Design-Labs
🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.
neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
Miladrzh/verilog-carry-lookahead-adder
Its my midterm project for Logic Circuit Course
salzhang/KoggeStone-Adder
A 32-bit Kogge-Stone Adder is implemented in this design.
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
ayushgupta98/ALU
An efficient multiplier and Accumulator (MAC) unit to do operations like multiplication & addition on numbers stored in RAM unit attached to it.
DoniaGameel/Verilog-adders-with-synthesis-using-Oasys
explore different implementations of adders and study their characteristics.
mostafa-elgendy22/Adder-Subtractor-Circuits
Parametrized Verilog implementation of different architectures of adder / subtractor circuits.
navidadkhah/ComputerArchitecture
Collection of Adders such as Ripple Carry and Carry Look Ahead
EmbeddedCamerata/32bits-CLA-and-ALU-Verification
32 bits CLA(Carry Lookahead Adder) and ALU RTL and verification. 32位块间超前的超前进位加法器及ALU设计与验证
jitendrasb24/Carry_Lookahead_Adder
Designing a 4-bit Carry Lookahead Adder using eSim
justin-marian/cla-16bits-adder
Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.
sushi0706/verilog-mini-projects
Verilog Mini Projects
Yellowflash-070/32-bit-Signed-Vedic-Multiplier
A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.
Yellowflash-070/BIST-for-6bit-CLA
A Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).
Amirreza81/Computer-Architecture
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
vinayak-tripathi/CAO
This repository contain CAO algorithms implemented in C language.
waterflow80/Carry-look-ahead-adder-HPC
Implementation of the Carry look ahead adder algorihtm, and parallizing the algorithm using OpenMP libriries
gubbriaco/digital-electronics-projects
Progetti di Elettronica Digitale 2021.
SoloSynth1/8BitCLA
Verilog for low delay 8-bit CLA with 4-bit lookahead circuits