cross-clock-domain

There are 3 repositories under cross-clock-domain topic.

  • dpretet/async_fifo

    A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

    Language:Verilog38712693

  • therealczr15/NYCU_ICLAB_2024S

    Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)

    Language:Verilog6100

  • arunbasilpaul/FIFO-Synchronous-vs-Asynchronous

    This project explores the simplicity / complexity of a synchronous and asynchronous FIFO. FIFO is a valuable component during data transmission, in particular during clock-domain crossing for multi-bit data. Therefore, we dive it into designing a synchronous and asynchronous FIFO to compare their similarities and differences.

    Language:VHDL