logic-design
There are 110 repositories under logic-design topic.
DrWaleedAYousef/Teaching
Teaching Materials for Dr. Waleed A. Yousef
ParhamP/Natural_Logic_Interpreter
Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic
shayanop/Water-Level-Meter
Water Level Meter
ysyesilyurt/Metu-CENG
All the homeworks, studies and projects I've done at Metu-CENG
beetlex-io/EventNext
EventNext is logic interface design actors components for .net core
ericm/newlogic
Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.
dreylago/logicmin
Logic Minimization in Python
kadircet/CENG
All the homeworks, testers and projects done at METU-CENG
fcayci/sv-digital-design
SystemVerilog examples for a digital design course
stdgregwar/elve
ELVE : ELVE Logic Visualization Engine
tunacinsoy/CSE
All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering
venkat-0706/codemind-c
As an Ignite Coder, solved numerous problems using C programming, demonstrating expertise in algorithms, problem-solving, and efficient coding for technical challenges.
VitorgsRuffo/Building-The-Hack-Computer
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
enesgarip/Projects
Projects of a CSE student at Marmara University
anthonyabeo/digital_circuits
A collection of digital logic circuits
asyncvlsi/chp2prs
Automated conversion from CHP to PRS using syntax-directed translation
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
AhmedHamed3699/AES-Encryption
An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog
marwan-9/digital-logic-circuits-simulator
Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.
alevkov/Karnau
A puzzle game for iOS.
DopeBiscuit/IEEE-Digital-IC-Design
This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.
ferhatozkan/Digital-Logic-Design-Project
University of Marmara, CSE3015 2018 Fall Project
michaelehab/Arithmetic-Logic-Unit-Project
Educational Project for Logic Design 1 course taken during Fall 2021 semester.
RezaGooner/Karnaugh-Map
The program in GUI that show and minimize with Karnaugh-Map in Python & C++
zeynepozalp/Coursework
Homeworks given at Department of Computer Engineering, Middle East Technical University.
andresrodriguez55/aSimple8-BitProcessor
Simple microprocessor in SystemVerilog.
matiasmicheletto/simcirjs
A SimCirJS fork with enhanced functionalities
3ein39/MultiSolver
The Idea is a gui program can solve most of the problems that faces students in courses like mathematics and physics And it also have another branch for helping the students with their time management and provide the students with materials
arashsm79/two-bit-multiplier
Two's complement two bit multiplier developed in Proteus
ImRanjbar/TeachingAssistant-Resources
A collection of assignments, workshops, and educational materials created during my teaching assistant journey at the University of Isfahan.
n1colasf/Obligatorio-DDA
Obligatorio Diseño y Desarrollo de Aplicaciones (Semestre 4 - Marzo 2023) Calificación: 36/40
upperdim/7segDispHex
Hexadecimal 7 segment display
ZeyadTarekk/Combinational-Multiplier
Combinational Multiplier Using verilog
AliAtaollahi/MaxNet-Network-Implementation-CAD-TA-Project
An implementation of the MaxNet network in Verilog, designed as a TA for the CAD course at the University of Tehran (Fall 2023)
shawntsai0312/NTUEE_SWITCHING_CIRCUITS_AND_LOGIC_DESIGN_21FALL_QUARTUS_LAB
NTUEE Switching Circuits and Logic Design 21Fall Quartus Lab
SpencerDeMera/8-Bit-ALU-Circuit
This project is my design of a basic ALU that can perform addition, subtraction, and bitwise logic operations. This project was designed in Logisim Evolution and implemented with TTL logic chips on breadboards.