/Arithmetic-Logic-Unit-Project

Educational Project for Logic Design 1 course taken during Fall 2021 semester.

MIT LicenseMIT

Arithmetic Logic Unit Project - Fall 2021

In this project, we designed and implemented an arithmetic unit that is capable of adding, subtracting and multiplying two signed numbers, and displays the result of the operation performed along with some additional flags regarding the operation and the result.

Diagram

Description

  1. Reminder: Result = A % B

    During the division A, B and Result are 3-bits signed numbers. A % 0 is forbidden and must output 0 and Div by Zero Flag must be asserted A % B, has the same sign as A.

    For example: +2%+3 =+2, +2%-3 =+2, -2%+3=-2, -2%-3=-2

  2. Remainder Circuit

  3. Multiplication: C = A * B

    During the multiplication, A and B are 3-bits signed numbers and C is a 5-bits signed number. The multiplication of 2-bits by 2-bits yields a result of 4-bits, therefore is composed of 4-bits for the value and 1-bit for the sign.

    For example: +2%+3 =+2, +2%-3 =+2, -2%+3=-2, -2%-3=-2

  4. Multiplication Circuit

  5. Addition: C = A + B

    During the addition, A, B, and C are all 3-bits signed numbers.

  6. Subtraction: C = A - B

    During the subtraction, A, B and C are all 3-bits signed numbers.

  7. Two's Complement Circuit Adder/Subtractor Circuit

Flags

  • Sign Flag:

    The sign flag indicates if the result is negative. The flag is set to 1 if the result is negative and 0 otherwise.

  • Zero Flag:

    The zero flag indicates if the result is zero. The flag is set to 1 if the result is zero and 0 otherwise.

  • Div by Zero Flag:

    The divide by zero flag indicates if we divide by zero. The flag is set to 1 if B operand equal zero in division operation and 0 otherwise.

Integration Circuit

Integration Circuit

🎉Finally Here's a celebration image!

Michael Ehab with the working project

Note : We used the logisim-7-segment-display-driver by marceloboeira during the simulation.