microarchitecture

google/cpu_features

A cross platform C99 library to get cpu features at runtime.

Dr-Noob/cpufetch

Simple yet fancy CPU architecture fetching tool

stong/how-to-exploit-a-double-free

How to exploit a double free vulnerability in 2021. Use After Free for Dummies

ShaneK2/inVtero.net

inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques

akhin/microarchitecture-cheatsheet

X86 CPU topics overview for developers , oriented towards performance

CMU-SAFARI/Pythia

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

HenrikBengtsson/x86-64-level

x86-64-level - Get the x86-64 Microarchitecture Level on the Current Machine

ucb-bar/saturn-vectors

Chisel RISC-V Vector 1.0 Implementation

Jerc007/Open-GPGPU-FlexGrip-

FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

codexlynx/hardware-attacks-state-of-the-art

Microarchitectural exploitation and other hardware attacks.

CMU-SAFARI/Hermes

A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)

Dr-Noob/peakperf

Achieve peak performance on x86 CPUs and NVIDIA GPUs

jiegec/cpu-micro-benchmarks

CPU micro benchmarks

libtea/frameworks

Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser

Dmitriy0111/nanoFOX

A small RISC-V core (SystemVerilog)

vhive-serverless/vSwarm-u

Framework that integrates the serverless benchmark suite vSwarm with gem5, the state-of-the-art research platform for system-and microarchitecture.

k-nuth/kth

High performance Bitcoin development platform

dhschall/gem5-fdp

Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5

CMU-SAFARI/Load-Inspector

A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786

yonseicasl/Kite

Kite: Architecture Simulator for RISC-V Instruction Set

b-shi/PMC-PMI

Performance Counter Measurements at the cycle granularity

dominiksalvet/risc63

Custom 64-bit pipelined RISC processor

kuby1412/RISC-V-MYTH-Workshop

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

AliLRS/RISC-V_Microprogrammed

FISC-Project/FISC-VHDL

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

toor1245/cpu_features.NET

.NET version of google/cpu_features to get cpu info at runtime.

MicroOperations/PredecodeRE

An analysis of intels goldmont plus uarch predecode caches core logic due to it being undocumented

evanlissoos/OISC

One Instruction Set Computer

forestfoxx/awesome-hardware-fuzzing

A curated list of research and repositories on the novel technique of hardware fuzzing

dominiksalvet/limen-alpha

Dual-core 16-bit RISC processor

dominiksalvet/super-riscv

Superscalar dual-issue RISC-V processor

mamadaliev/sequent

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

aecsocket/cpu-features-java

Java bindings for Google cpu_features

hushon/Tiny-RISCV-CPU

Mini RISC-V CPU

saintube/gem5-dscp

DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.