CMU-SAFARI/Hermes
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
C++MIT
Issues
- 3
Hello. I want to conduct an eight-core experiment with the configuration shown below. How to configure the script about "./build_champsim.sh glc multi multi multi multi 1 1 0"?
#24 opened by szuhzw - 0
Bug in CLOffset feature processing
#35 opened by rahulbera - 0
Trace links in artifact_traces.csv are obsolete
#33 opened by nmd1411 - 0
Hello. I did not see the "prefetch_line" function being called in the SMS.CC and SMS.h files. May I ask in which code segment the prefetch addresses generated by the SMS prefetcher are submitted to the processor for data prefetching
#28 opened by szuhzw - 3
Hello. Is the prefetcher (Pythia Bingo SPP MLOP SMS) in the paper responsible for prefetching data from main memory to the cache hierarchy?
#26 opened by szuhzw - 1
Hello. When I run the trace generated by me, it shows a failure like below. Please tell me what is the reason for this and how to solve it?
#25 opened by szuhzw - 8
- 8
Excuse me. When I running McPAT according to the process, the following situation occurs. How to resolve it?
#22 opened by szuhzw - 0
- 2
- 0
These are errors in the automate_rollup.sh. It should be Fig.9, Fig.12, Fig.14 and Fig.17b
#17 opened by szuhzw - 3
- 2
Hello. Does the "Offset" means Cacheline offeset? Does the "CLOffset" means byte offset?
#13 opened by szuhzw - 1
- 1
- 2
Asking for Experiments Results
#1 opened by YangHangWu - 1
- 2
- 0
Small typo in the main README.md file
#3 opened by jesuisalexjamet