SAFARI Research Group at ETH Zurich and Carnegie Mellon University

DAMOV

DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)

MQSim

MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)

prim-benchmarks

PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (https://arxiv.org/abs/2105.03814).

Pythia

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

ramulator-pim

A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

rowhammer

Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf.

SoftMC

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf>

SparseP

SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) architectures. SparseP is developed to evaluate and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by C. Giannoula et al. [https://arxiv.org/abs/2201.05072]

CMU-SAFARI/MQSim

MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)

CMU-SAFARI/ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

CMU-SAFARI/prim-benchmarks

PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (https://arxiv.org/abs/2105.03814).

CMU-SAFARI/Pythia

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

CMU-SAFARI/Hermes

A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)

CMU-SAFARI/PiDRAM

PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system implemented on an FPGA. Described in our paper: https://arxiv.org/abs/2111.00082

CMU-SAFARI/DRAM-Bender

DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

CMU-SAFARI/RawHash

RawHash can accurately and efficiently map raw nanopore signals to reference genomes of varying sizes (e.g., from viral to a human genomes) in real-time without basecalling. Described by Firtina et al. (published at https://academic.oup.com/bioinformatics/article/39/Supplement_1/i297/7210440).

CMU-SAFARI/RowPress

Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomenon in DRAM that is different from RowHammer. Described in our ISCA'23 paper by Luo et al. at https://people.inf.ethz.ch/omutlu/pub/RowPress_isca23.pdf

CMU-SAFARI/AirLift

AirLift is a tool that updates mapped reads from one reference genome to another. Unlike existing tools, It accounts for regions not shared between the two reference genomes and enables remapping across all parts of the references. Described by Kim et al. (preliminary version at http://arxiv.org/abs/1912.08735)

CMU-SAFARI/Virtuoso

Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.

CMU-SAFARI/Load-Inspector

A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786

CMU-SAFARI/ABACuS

New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresholds, as described in the USENIX Security'24 paper https://arxiv.org/pdf/2310.09977.pdf

CMU-SAFARI/MIMDRAM

Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing''. Paper is at: https://arxiv.org/pdf/2402.19080.pdf

CMU-SAFARI/Genome-on-Diet

Genome-on-Diet is a fast and memory-frugal framework for exemplifying sparsified genomics for read mapping, containment search, and metagenomic profiling. It is much faster & more memory-efficient than minimap2 for Illumina, HiFi, and ONT reads. Described by Alser et al. (preliminary version: https://arxiv.org/abs/2211.08157).

CMU-SAFARI/FCDRAM

Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR operations in real DDR4 DRAM chips. Described in our HPCA'24 paper by Yuksel et al. at https://arxiv.org/abs/2402.18736

CMU-SAFARI/EINSim

DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.

CMU-SAFARI/SiMRA-DRAM

Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 rows in real DDR4 DRAM chips. Described in our DSN'24 paper by Yuksel et al. at https://arxiv.org/abs/2405.06081

CMU-SAFARI/CoMeT

CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper https://arxiv.org/pdf/2402.18769.pdf

CMU-SAFARI/HBM-Read-Disturbance

Detailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new takeaways, as described in the DSN'24 paper https://arxiv.org/pdf/2310.14665.pdf

CMU-SAFARI/Sectored-DRAM

A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (ii) activating a disproportionately large number of DRAM cells at low cost. Described in our paper https://arxiv.org/pdf/2207.13795.

CMU-SAFARI/RawAlign

RawAlign is a real-time raw nanopore read mapper based on the Seed-Filter-Align paradigm as described by Lindegger et al. (https://arxiv.org/abs/2310.05037)

CMU-SAFARI/SelfManagingDRAM

Source code for evaluating the performance and DRAM energy benefits of Self-Managing DRAM (SMD), proposed in https://arxiv.org/abs/2207.13358

CMU-SAFARI/BreakHammer

CMU-SAFARI/MetaTrinity

MetaTrinity is a novel metagenomic analysis tool employing efficient containment search techniques and heuristics for read mapping to achieve significant speedup while maintaining high accuracy. This positions MetaTrinity as an efficient solution, optimally balancing speed and precision in metagenomic analysis.

CMU-SAFARI/Rubicon

RUBICON is a novel framework to automatically develop deep-learning-based genomic basecallers for any given architecture, as described in our Genome Biology'24 paper https://genomebiology.biomedc

CMU-SAFARI/PIM-Opt

Source code & scripts for distributed machine learning training workloads on a real-world Processing-In-Memory system (i.e., UPMEM). Described in our PACT'24 paper by Rhyner et al. at https://arxiv.org/pdf/2404.07164v2

CMU-SAFARI/SequenceLab

SequenceLab is a benchmark suite for evaluating computational methods for comparing genomic sequences, such as pre-alignment filters and pairwise sequence alignment algorithms. SequenceLab is described by Rumpf et al. at https://arxiv.org/abs/2310.16908

CMU-SAFARI/rawasm

Rawasm is a patch to the popular miniasm tool. It enables the construction of genome assembly from raw nanopore signals.

CMU-SAFARI/PyGim