CMU-SAFARI/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
C++MIT
Issues
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memory tick function of DDR3 configuration
#120 opened by JimmyWong1998 - 2
Problem with Ramulator.
#112 opened by zhizunbaowhy - 1
DRAM trace mode: No mechanism to identify the arrival time of the requests
#106 opened by HarshVardhanKumar - 0
multi-core simulation has a problem in handling writebacks for cache filtered mode
#119 opened by FanosLab - 2
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the cycle for DDR4 need to be updated
#118 opened by alinezhad2018 - 2
Possible wrong address mapping
#115 opened by shenjiangqiu - 0
Execution getting killed when running using Zsim trace file with 2 billion instructions.
#117 opened by satanu01 - 4
gem5 version 10231 now is unavailable
#103 opened by asd055189 - 2
Error while using Trace Generator tool in Ramulator
#116 opened by Upasna55 - 0
No rule to make target 'obj/.depend'
#114 opened by czh-rot - 0
Problem with Ramulator
#113 opened by zhizunbaowhy - 2
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Heterogeneous Memory can be used in Ramulator?
#111 opened by m1chaelyeung - 0
Why is update_serving_requests for WRITE requests called at the time when they are issued to the DRAM?
#102 opened by beta-47 - 4
core dumped
#101 opened by hanm2019 - 0
GDDR5 channel_width should be 32, not 64
#107 opened by salvadorpetit - 0
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- 1
Assert Error When Running FCFS Policy
#98 opened by psoni357 - 0
Self Refresh and Refresh Wrong Prerequisites
#100 opened by TheAhmad - 0
deploy rowhammer in the ramulator
#99 opened by coreader - 0
multi-core optimization
#97 opened by zhangliang1997 - 1
memory trace Driven
#93 opened by sac2019 - 0
confused about the mappings
#96 opened by xvhan - 0
Generate dram.trace from gem5
#95 opened by HaFred - 0
Mapping file
#94 opened by qhuppert - 2
request.depart set to 0 when created
#89 opened by hanm2019 - 0
questions regarding building hybrid memory
#87 opened by wenzez - 0
- 1
Question regarding PCM behavior
#85 opened by chohy - 1
Question ragarding simulating a DIMM
#84 opened by benMen87 - 0
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Power-Down Management
#80 opened by lsteiner-tukl - 1
Question about channels widths
#77 opened by colleenfyj - 1
Wrong timing calculation in Ramulator
#79 opened by allencho1222 - 1
Read to Write timing is seemingly violated
#78 opened by abagchi - 1
Compile Error:q
#64 opened by SarahFz89 - 0
Ramulator setup with recent Gem5 Version
#66 opened by amanm2 - 0
ramulator support multiple channels
#73 opened by tks2004 - 0
`using namespace std` in headers
#71 opened by mrj10 - 0
Why the CPU trace is the decimal address??
#70 opened by ZhangXian1010 - 5
What is the length of one read request?
#55 opened by Cassiel-girl - 5
On the fly burst mode
#67 opened by marcodamico - 3
Burst mode
#65 opened by marcodamico - 0
Ramulator Latency Calculation
#68 opened by SarahFz89 - 3
L1L2 Cache Config
#63 opened by SarahFz89 - 1
Support for DDR4 2666V 16GB x4
#60 opened by tks2004 - 0
Cannot run the sample command
#56 opened by nipunagarwala