Read to Write timing is seemingly violated

[abagchi]

I see a write request immediately after a read request. Don't we have some minimum gap requirement due to the shared data bus?

[~/ramulator]$ ./ramulator configs/LPDDR4-config.cfg --mode=dram dram.trace
ACT 1: 0 0 2 4660 45
ACT 2: 1 0 2 19645 45
RD 23: 0 0 2 4660 45
ACT 24: 0 0 3 13780 30
WR 24: 1 0 2 19645 45
ACT 25: 1 0 7 26991 26
RD 46: 0 0 3 13780 30
ACT 47: 0 0 5 30838 31
WR 47: 1 0 7 26991 26
RD 69: 0 0 5 30838 31

[RSpliet]

The default LPDDR4 configuration is configured with two channels. I presume the trace format is
<cmd> <cycle>: <ch> <rank> <bank> <row> <col>
Under this presumption it seems that the two commands are non-conflicting as they address different channels.