confused about the mappings
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xvhan commented
I read row_interleaving.map
in ./mappings
and found that the number of bits is 41. But the address width in dram.trace
is 32 bit . I am a little confused about that.Does this imply that the invisible higher 9 bits of requested address in dram.trace
are all set to be zero ?
And from the requests in the dram.trace
I conclude that all requests should be 64-byte aligned,which means the lower 6 bits of every requested address should be set to zero ?Please correct me if I am wrong.