mips-processor
There are 105 repositories under mips-processor topic.
mhyousefi/MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
aeris170/MARS-Theme-Engine
It's all coming back into focus!
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Ingenic-community/linux
Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.
edoardottt/asm-snippets
Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:
jasonlovescoding/MIPS32CPU-5stage-pipelined
A 5-stage pipelined mips32 processor
yasnakateb/PipelinedMIPS
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
hakula139/MIPS-CPU
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
JosiahMendes/MIPS32-T501
A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.
yasnakateb/MIPSProcessor
🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
holden-davis-uca/MARS-UCA
Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.
LIU42/Processor
《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
mongrelgem/cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
pariyajebreili/PipelinedMipsProcessor
A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.
alabarjasteh/fum-mips
MIPS simulator written in Go
flozzone/DDCA
Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.
SentinelSw/MipsStaticStackAnalyzer
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
akankshac-073/MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
daltonbr/MIPS
simulator of a MIPS processor in C
Gripnook/mips-pipelined-processor
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
z64me/minimips64
the tiniest MIPS R4300i assembler and disassembler
aeris170/Dark-Side-of-MARS
DEPRECATED!!! An (almost) fully functional theme engine for MARS.
cwalk/Mini-Processor-Simulator
Core part of a mini processor simulator called MySPIM using the C language on a Unix/Linux platform. MySPIM demonstrates some functions of the MIPS processor as well as the principle of separating the data-path from the control signals of the MIPS processor. The MySPIM simulator reads in a file containing MIPS machine code (in a specified the format) and simulates what MIPS does cycle-by-cycle (single-cycle data path).
nimaiji/MIPS-Pipeline-CPU
💻 MIPS Pipeline Processor simulator
anupbhowmik/Computer-Architecture-CSE-306
This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.
lone0/buildroot-x2000
Buildroot for Halley5, the evaluation board for Ingenic X2000 SoC
psh4607/32-bit-MIPS-Processor-Pipeline
A 32-bit MIPS processor developed in Verilog based on pipeline
arlotfi79/MIPS-Processor
A 32-bit MIPS Processor Implementation in Verilog HDL
fardinanam/CSE-306-Computer-Architecture-Sessional
Assignments done in CSE306 course offered by CSE, BUET
guntas-13/mips-processor-basys3
Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor
JonayedMohiuddin/8bit-PIPELINED-MIPS
An 8-bit MIPS processor designed in Logisim, featuring pipelined and non-pipelined architectures, a custom assembler for MIPS assembly to binary conversion, extended I/O peripheral support, and some playable Game implemented in MIPS assembly.
kalhorghazal/Mips-MultiCycle
Mips Multi-Cycle, Computer Architecture course, University of Tehran
mateuspinto/FPGA_SystemVerilog_MIPS_Pipeline-TP1-OC2-UFV
A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.