multiplier
There are 73 repositories under multiplier topic.
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
antonblanchard/vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
suoglu/Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
greenelab/multi-plier
An unsupervised transfer learning approach for rare disease transcriptomics
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
contributte/forms-multiplier
:repeat: Form multiplier & replicator for Nette Framework
scale-lab/DRUM
The Verilog source code for DRUM approximate multiplier.
RaulMurillo/Flo-Posit
Posit Arithmetic Cores generated with FloPoCo
rcetin/booth_wallace_multiplier
Booth encoded Wallace tree multiplier
pub-calculator-io/lcm-calculator
Free WordPress Plugin: LCM calculator to find the LCM of two or more numbers. Shows solutions by prime factorization, common multiples, cake/ladder, GCF, division, and Venn diagram. www.calculator.io/lcm-calculator/
tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
gagan405/WallTree
A VHDL code generator for wallace tree multiplier
Saadia-Hassan/8x8Multiplier-Using-Vedic-Mathematics
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
Hassan313/Approximate-Multiplier
This repository contains approximate 8-bit multiplier Verilog code.
suoglu/Carry-Save-Multiplier
Parameterized and 4-bit carry save multiplier design
suoglu/Integer-Multiplier-Hardware-Parameterized
Source code for pure combinational 16 bit integer multiplier hardware
mnb27/Fast-Multipliers
32-bit Wallace and Dadda Tree Multiplier
SDibla/VHDL-Booth_Multiplier
Booth's algorithm is a procedure for the multiplication of two signed binary numbers in two's complement notation. This code is a structural\behavioral implementation of the N bit Booth's multiplier in VHDL.
gustavohb/booth-multiplier
VHDL implementation of the Booth's multiplication algorithm
himingway/Parallel_Multiplier
A Parallel Multiplier Using SystemVerilog HDL
MohammadNiknam17/Signed-4BIT-Binary-Multiplier_VHDL-FPGA
These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.
zpekic/sys_primegen
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
anand873/DigitalVLSI
This repository consists of verilog codes for Digital VLSI Lab (EC39004), IIT KGP.
arashsm79/two-bit-multiplier
Two's complement two bit multiplier developed in Proteus
BlooketHeck/Claculators
A few calculators using python!
GridSAT/CNF_FACT-MULT
CNF Generator for Factoring Problems
jpsimas/mbe-dadda-vhdl
Generator for unsigned n-bit modified Booth encoding Dadda tree multiplier code in VHDL written in C++. Based on https://github.com/HSOgawa/fast-multipliers/.
kotharipeddirajulu/4bit_multiplier_using_4bit_full_adder_VHDL
This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled.
levindoneto/4x4-Multiplier-VHDL
A 4x4 Multiplier with matrices on memories built for running on an FPGA, which uses two single-port memories with 4 positions of 16 bits each for the input matrices and one single-port memory.
nicolavianello95/DLX
Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
nicolavianello95/mult32_MBE_dadda
Design and VHDL description of a 32bit multiplier using a Modified Booth Encoding and a Dadda CSA tree.
pmichaillat/countercyclical-multiplier
Code and data for the paper "A Theory of Countercyclical Government Multiplier"
sourabhjain19/Booth-s-Multiplier
COA OEE (ASM)
andrea-varesio/smart-dca-backtest
Smart Dollar Cost Averaging backtest
pmichaillat/stimulus-spending
Code and data for the paper "Optimal Public Expenditure with Inefficient Unemployment"