pipelined-risc
There are 6 repositories under pipelined-risc topic.
sudhamshu091/Single-Cycle-Risc-Pipelined-Processor-Verilog
Single Cycle MIPS Pipelined Processor using Verilog
ZeyadTarekk/RISC-Pipelined-Processor
5 stages RISC pipelined processor following Harvard architecture.
avikram2/RISCVPipelinedProcessor
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
PaletiKrishnasai/Computer-Architecture
Hardware designs modelled with verilog
SaiManojGubbala/RISC-V
A 32 Bit RISC-V Processor Implementation in Verilog
omkar-nitsure/Pipelined-Processor-Design
Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL