processor-architecture
There are 182 repositories under processor-architecture topic.
intel/pcm
Intel® Performance Counter Monitor (Intel® PCM)
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
jbush001/NyuziProcessor
GPGPU microprocessor architecture
hlorenzi/customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
Mariotti94/WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
jmuehlig/perf-cpp
Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.
sstsimulator/sst-elements
SST Architectural Simulation Components and Libraries
tscheipel/HaDes-V
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
caleb531/cache-simulator
A processor cache simulator for the MIPS architecture
physical-computation/sunflower-embedded-system-emulator
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
sdasgup3/parallel-processor-design
Super scalar Processor design
ShichenQiao/ECE554_SP23_FPGA_Handwriting_Recognition
Senior Design Project at UW-Madison ECE
Amey-Thakur/COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
alexander-titov/public
A collection of my cources, lectures, articles and presentations
GodTamIt/tomasulo-simulation
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
Mograsim-Team/Mograsim
Modular Graphical Simulator for Teaching Microprogramming
GeekAlexis/superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
meiniKi/RV32I_SC_Logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
Danijel-Korent/RISC-V-emulator
RISC-V emulator/simulator in Python
aitesam961/16-Bit-RISC-Core-Processor
A RISC custom-ISA, 16-Bit Processor
digital-design-snu/RNBIP_SingleBusProcessor
Single Bus Processor - Summer Project 2016
luk3Sky/Building-A-Processor---Project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
pariyajebreili/32BitMipsProcessor
An Implementation of MIPS processor with single cycle architecture using Verilog.
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
worthant/OPD
:computer: This course is about computer science basics.
arda-guler/TurnaCore
An imaginary 16-bit CPU architecture with custom assembly language and instructions
arxiver/Pipelined-MIPS
MIPS Pipelined CPU simulation using VHDL language
kara-abdelaziz/SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
thenamangoyal/RISC-Simulator
A C++ pipeline based simulator of RSIC architecture.
trexxet/virtaxy-vm
Flexible functional simulator and assembler for user-defined architectures
linguini1/gol-16
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
maxislash/Tomasulo
Python simulator of Tomasulo algorithm
the-pinbo/MIPS-5-Stage-Pipeline-Project
This project involves the implementation and simulation of a MIPS 5-stage pipelined processor using Verilog. The implementation is based on the MIPS architecture as outlined in the "Computer Organization and Design: The Hardware/Software Interface" and "Digital Design and Computer Architecture"