processor-design

There are 71 repositories under processor-design topic.

  • mips32-modified

    Language:Verilog

  • DL-UNTREF---TP-Procesador

    Language:VHDL

  • Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

    Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

    Language:Verilog

  • COL216-Computer-Architecture

    Course assignments of COL216:- Computer Architecture course at IIT Delhi under Professor Kolin Paul

    Language:VHDL

  • nodecsv

    Projeto de leitura e processamento de dados de CSV em Node.js.

    Language:JavaScript

  • EN2031-Computer-Organization-and-Design

    This includes assignments related to EN2031 - Computer Organization and Design semester 3 module at ENTC,UoM.

  • 3-stage-pipelined-32-bit-Processor-RISC-V-ISA-

    Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture

    Language:SystemVerilog

  • pipe-MIPS32

    It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.

    Language:Verilog

  • SimpleProcessor

    Simple Single Bus RISCV Processor

    Language:SystemVerilog

  • 5-stage-pipelined-32-bit-Processor-RISC-V-ISA-

    Implementing a 32-bit processor using RISC-V architecture.

    Language:SystemVerilog

  • MARS-Web-App

    This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

    Language:JavaScript

  • 32-Bit-Non-Pipelined-Single-Cycle-Processor

    This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

    Language:SystemVerilog

  • FUM-Computer-Architecture-FUM-MIPS-Procssor-Design-Project-Desceription-TA

    Computer Architecture Project Description

    Language:TeX
  • FUM-Computer-Architecture-Pipelined-MIPS-Processor

    FUM-Computer-Architecture-Pipelined-MIPS-Processor

    Pipelined MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad

    Language:Verilog

  • FPG8

    Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA

    Language:Verilog

  • MIPS-Processors

    CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations

    Language:Python

  • processor-design

    Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)

    Language:SystemVerilog

  • risc-processor

    A 2-stage pipeline processor implemented in C++.

    Language:C++

  • SingleCycleMIPS-Implementation

    Designed the revised single-cycle datapath and revised control units which make a processor that executes the instructions as well as the instructions implemented already in the design.

    Language:Verilog

  • COL216-Computer-Architecture

    Course repository for Computer Architecture, IIT Delhi 2021-22

    Language:VHDL

  • multi-core-processor

    Multi-core Processor Design for Matrix Multiplication Using Verilog

    Language:Verilog

  • z80-verilog-report

    Verilog Implementation of a Z80 Compatible Processor Architecture - Lab Report

    Language:TeX

  • computer-organization-basics

    Computer Organization (INF-UFRGS)

  • DSD_processor

    A synthesizable pipelined RISC-V processor. (Digital System Design, Spring 2020, NTUEE)

    Language:Verilog

  • R8-core_FPGA_microcontroller

    Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis

    Language:Assembly

  • Computer-Architecture-CSE-306-BUET

    Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET

    Language:VHDL

  • research

    high instruction-level-parallelism (ILP) using Resource-Flow-Execution

    Language:C