pynq-z2
There are 42 repositories under pynq-z2 topic.
sefaburakokcu/quantized-yolov5
Low Precision(quantized) Yolov5
andre1araujo/YOLO-on-PYNQ-Z2
This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.
sefaburakokcu/finn-quantized-yolo
Low-Precision YOLO on PYNQ with FINN
MakarenaLabs/Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
junwha0511/MNIST-FPGA-Accelarator
MNIST accelerator using pynq-z2 and the binary qunatization
kuoyaoming93/sem-ip_pynq
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
reed-foster/pynq-audio
RTL and python for using the ADAU1761 audio codec on the Pynq-Z2 board from TUL
franout/tensorflow_for_pynqz2
tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry
XAli-SHX/FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm
FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)
Gabriele-bot/FPGA_projects
Some of my projects/mistakes on various FPGA boards
berniGelectronic/FPGA_Multimedia_Player
MSc Final Project
Gabriele-bot/PYNQ_IA
Repository that contains some neural network inferences on PYNQ-Z2 board employing hls4ml
PCov3r/FPGA_Handwritten_digit_recognition
A Verilog implementation of a hand-written digit recognition Neural Network
Sanjay-A-Menon/FES256
A fast and efficient implementation of a SHA256 cracker
dsa-shua/FPGA-SystolicArray
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
Prithvish04/reconfigurable_project
Canny edge detection in HLS
Sumegh-git/Xilinx-Innovation-Challenge
Team reverse_biased
ChienKaiMa/2021_ACA_HLS_team05
High level synthesis projects and practices
cpantel/TheZynqBook
Exercises from the book
franout/Cogitantium
Hardware Accelerator for ML
gubbriaco/FPGA-VHDL-filtering-circuit-grayscale-images
A project that involves the hardware design (VHDL) of a circuit on FPGA that performs the filtering of an image through an isotropic filter. The circuit is also tested and validated (both from the point of view of the error and from the point of view of the quality of the filtering) through procedures described in MATLAB.
kuoyaoming93/axi_uartlite_pynq
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
Logicademy/PYNQ-SoC-Builder
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
mariodruiz/PYNQ_tutorials
PYNQ Tutorials
PoliTo-ASAC-Lab/ASAC_CPM
ASC_CPM is a Cluster Power Manager solution, to be used for testing purposes or extensive fault injection campaigns involving a cluster of devices. (Daniele Rizzieri - 2023)
ZeroX29a/PynqZ2
Complete collection of general resource of Pynq Z2
abidanBrito/fpga-polymul
Polynomial multiplier for the Xilinx Pynq-z2 board.
PoliTo-ASAC-Lab/PYNQ_UARTopus
Python platform to use a TUL PYNQ-Z2 development board to virtualize up to 12 UART connections (tx+rx@9600bps) over TCP-IP
rishz09/digital-safe-verilog
A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
saulcarvalho/CE_Modulator_FSK_PSK
2023. FSK and PSK modulators done in PYNQ-Z2 board for the class of Configurable Electronics.
axelvanherle/IoTProject_1
By Sem Kirkels, Nathan Bruggeman, Indy Penders and Axel Vanherle. This sends a random value from the pynq to a server running openremote.
gubbriaco/VHDL_scripts
Useful VHDL scripts for hardware description.
riyasach189/Vitis_HLS_2022.1_Examples
This is a collection of some examples designed in the Vivado Design Suite.