questasim
There are 29 repositories under questasim topic.
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
Paebbels/JSON-for-VHDL
A JSON library implemented in VHDL.
MJoergen/HyperRAM
Portable HyperRAM controller
WajahatRiaz/QuadSPI
RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
Ghonimo/Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
htminuslab/Modelsim-Unicorn
Modelsim QEMU Unicorn integration via the FLI
MJoergen/Avalon
Utilities for Avalon Memory Map
Paebbels/pyIPCMI
A Python-based IP Core Management Infrastructure.
dave2pi/SublimeLinter-contrib-vlog
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
yuravg/eda-scripts
Collection of scripts for EDA tools
jevogel/SublimeLinter-contrib-modelsim
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
yuravg/color_questasim
A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.
Abdelrahman1810/SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
AlPrime2k1/Finite-State-Machines
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
teekamkhandelwal/Uart_tx_main
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.
aaronrjmanj/verilog
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
cad-polito-it/r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
dave2pi/SublimeLinter-contrib-vcom
SublimeLinter plugin for linting VHDL with Modelsim vcom
kropotin4/SystemVerilog-examples
Попытка написать несколько примеров кода на языке SystemVerilog.
NikosDelijohn/finjenv
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
sbaldzenka/uart_core
UART IP-core for FPGA.
hcshires/MIPS-Processors
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
nekiicheb/fpga_solution_of_test_assignment
A solution of test assignment from company
Abdelrahman1810/RTL-Verification-of-AMBA3_4-APB-Protocol
This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.
flfl04/UART_Verilog
UART 8-Bit Verilog Simple Realization
habibhossam/SPI-Slave-with-Single-Port-RAM
Designing SPI Slave with Single Port RAM using questasim and vivado.
lazarvulic99/SystemVerilog-Verification---Register-functionalities
Simple register realisation for SystemVerilog Verification