systolic-arrays
There are 25 repositories under systolic-arrays topic.
trevorpogue/algebraic-nnhw
Deep learning accelerator architectures requiring half the multipliers
aliemo/transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
UCLA-VAST/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
rejunity/tiny-asic-1_58bit-matrix-mul
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
diwu1990/uSystolic-Sim
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
horizon-research/systolic-array-dataflow-optimizer
A general framework for optimizing DNN dataflow on systolic array
IntelLabs/t2sp
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
maao666/HPDLA
Systolic-array based Deep Learning Accelerator generator
ic-lab-duth/FusedGCN4HLS
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
jasonlin316/Systolic-Array-for-Smith-Waterman
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
AIC2021/AIC2021_TPU_Template
Template for project1 TPU
alex-mckenna/clash-systolic
Systolic Networks in Clash
KevinWang96/EE599_YihaoWang_7410178057
EE599 Accelerated Computing on FPGA
gultai4ukr/PySAGS
Systolic arrays graphical simulator (SAGS), written in Python.
YuFengUofR/dataflow_optimizer
A general framework for optimizing DNN dataflow on systolic array
anthonyarusso/systolic-array
SystemVerilog module for matrix multiplication
dsa-shua/FPGA-SystolicArray
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
joulook/Parallel-Processing-Spring-2021
In this repository you can find all of my projects for Parallel Processing Course when I was in 2nd semester of my master's at SUT.
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
RayWright27/SystemC-CNN-test-model
This is an unfinished test model of CNN, based on cnn.h5 Keras pretrained model EN10/KerasMNIST@4ef71d6/cnn.h5 .
Awrsha/FPGA-Programming
This repository contains a collection of projects focused on implementing various deep learning models and algorithms on FPGA. These projects leverage the power of FPGA for efficient and high-performance execution of machine learning tasks.
kevin861222/general-purpose-4x4-TPU
A simplified 4X4 TPU
EMITLabGit/PsuedoSim
Analytical modeling tool for CNNs running on array-based accelerators.
NeuroFan/SystolicArray
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
sebyss/Visual-representation-of-systolic-arrays
Visual representation of how systolic arrays made in Unity3d. (Just code)