tang-nano-9k

There are 12 repositories under tang-nano-9k topic.

a2fpga/a2fpga_core
Apple II FPGA Co-Processor
Language:F#37 7 44
charkster/usb_pd_monitor
USB PD cc pin monitor implemented in a Tang Nano 9K FPGA.
Language:SystemVerilog15 4 01
calint/tang-nano-9k--riscv--cache-psram
RISC-V implementation of rv32i for FPGA board Tang Nano 9K utilizing on-board burst PSRAM and flash
Language:Verilog7 1 01
vossstef/VIC20Nano
Commodore VIC20 core for the Tang Nano 20k Primer 20k Primer 25k Nano 9k Mega138k Pro FPGA
Language:VHDL7 3 51
vossstef/tang_nano_9k_6502
6502 SBC in a Gowin GW1NR-9 FPGA on a Sipeed Tang Nano 9k
Language:VHDL6 2 10
vossstef/tang_nano_9k_vic20_hdmi
Commodore VIC-20 core for the Tang Nano 9k FPGA
Language:VHDL6 1 30
charkster/tang_nano_9k-uart_block_ram
UART interface to a block ram in the Tang Nano 9k FPGA. No pin connections needed, just use the USB UART.
Language:SystemVerilog5 3 01
muzhiyun/Tang_9K_HDMI
HDMI for Tang Nano 9K
Language:SystemVerilog5 1 00
vossstef/tang_nano_9k_vic20_lcd
Commodore VIC20 core for the Tang Nano 9K FPGA with LCD Output
Language:VHDL5 2 00
tmssngr/z8verilog
Zilog Z8 softcore in verilog
Language:SystemVerilog3 1 00
charkster/tang_nano-trigger_uart
This is a re-write of my previous trigger project. This time Tang Nano 9k is the target hardware and the USB UART is used to configure and enable triggering.
Language:SystemVerilog2 1 01
calint/tang-nano-9k--riscv
experiments with simple CPU design
Language:Verilog1