verilog-code
There are 111 repositories under verilog-code topic.
snbk001/Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
TheSUPERCD/8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
benitoss/UnAmiga
Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA
Arjun-Narula/Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
mihir8181/VerilogHDL-Codes
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
aklsh/getting-started-with-verilog
Verilog modules for beginners
geraked/verilog-rle
Verilog Implementation of Run Length Encoding for RGB Image Compression
aut-ce/CE202-LC-Lab-Manual
Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
aditeyabaral/DDCO-Lab-UE18CS207
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
djzenma/RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
jge162/verilog_compiler
Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.
NellyW8/VeriReason
This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
vasanthkumar18/Cache-Compression
Cache compression using BASE-DELTA-IMMEDIATE process in verilog
siri-n-shetty/iverilog
This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).
pratikbhuran/Voting_Machine
Voting machine implemented in verilog
mahdizynali/verilog-digital-circuit-codes
simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
mongrelgem/UART-RTL-Physical-Design
Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2
Code-Sample-Collection/VerilogHDL-Practical-insights
<轻松成为设计高手: VerilogHDL 实用精解> EDA 先锋工作室, 王诚, 吴继华 2012.6
EhsanShahbazii/Digital-VLSI-System-Design-Projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
mseminatore/fpgacoding
Source code companion to the fpgacoding.com blog
vSasakiv/RV32I_Processor
Risc-V 32i processor written in the Verilog HDL
sts08015/HDLBits_solution
My own HDLBits solution :)
Dhruv0Upadhyay/100_Days_of_RTL
100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog
foodinsect/Advanced-Practice
This repository contains a collection of small Verilog modules for various purposes.
GirloftheLimberlost/DigitalLockFPGA
FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)
trojanink/University-projects
Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.
ukashasohail/MIPS_32bit_SCDP_Verilog
An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.
yuri-panchul/tt08-adder-with-flow-control
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
hwlabnitc/hwlabnitc.github.io
Main website of the HW Lab guide by NITC
janilaunonen/iCEblink40-examples
Simple example programs for the Lattice iCEblink40-HX1K Evaluation Kit in Verilog for fun and learning.
mircea-pavel-anton/VHDL-Decryption
A small decryption module, written in Verilog, as a university assignment.
PXVI/std_module
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
samiyaalizaidi/Direct-Digital-Synthesizer
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
MohammedS2lah/HDLBits_Verilog_Tutorials
Welcome to my repository, where I provide solutions to Verilog challenges from the HDLBits website