verilog-project

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

adibis/DDR2_Controller

DDR2 memory controller written in Verilog

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

ashishrana160796/verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

prajwalgekkouga/AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

xiazhuo/nscc2022_personal

NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

vedic-partap/Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

mihir8181/VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

Akashtailor-exe/30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

ultraembedded/minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

adibis/Interrupt_Controller

An 8 input interrupt controller written in Verilog.

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

coole198669/viterbi_decoder

Hardware Viterbi Decoder in verilog

RPG-7/HGA101_GPU

tongplw/Undertale-Verilog

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

mnmhdanas/DA-Based-LMS-Adaptive-filter

Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

pendkeomkar/SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

lorentsinani/16bitCPU-Verilog

16 bit CPU created in Vivado with Verilog

flasonil/Serial-Multiplier

16 bit serial multiplier in SystemVerilog

sudhamshu091/RISC-Pipelined-Processor-32-bit-Verilog

Simple Pipelined 32 bit RISC Processor

sudhamshu091/Single-Cycle-Risc-Pipelined-Processor-Verilog

Single Cycle MIPS Pipelined Processor using Verilog

aekanshd/booths-multiplier-using-verilog

powerplayer9/Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

emrealci/FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

vasanthkumar18/Cache-Compression

Cache compression using BASE-DELTA-IMMEDIATE process in verilog

cw1997/SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

pratikbhuran/Voting_Machine

Voting machine implemented in verilog