verilog-project

There are 278 repositories under verilog-project topic.

  • Gowtham1729/Image-Processing

    Image Processing Toolbox in Verilog using Basys3 FPGA

    Language:VHDL2183241

  • snbk001/Verilog-Design-Examples

    Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

    Language:Verilog1612029

  • zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

    Language:Verilog1435337

  • neelkshah/MIPS-Processor

    5-stage pipelined 32-bit MIPS microprocessor in Verilog

    Language:Verilog1354115

  • michaelehab/AES-Verilog

    Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

    Language:Verilog1212628

  • adibis/DDR2_Controller

    DDR2 memory controller written in Verilog

    Language:Verilog788032

  • mongrelgem/Verilog-Adders

    Implementing Different Adder Structures in Verilog

    Language:Verilog752016

  • xiazhuo/nscc2022_personal

    NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

    Language:VHDL75004

  • prajwalgekkouga/AHB-to-APB-Bridge

    The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

    Language:Verilog681216

  • ashishrana160796/verilog-starter-tutorials

    Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

    Language:Verilog611021

  • TheSUPERCD/8bit_MicroComputer_Verilog

    This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

    Language:Verilog591015

  • Akashtailor-exe/30-days-of-verilog

    30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

    50106

  • Arjun-Narula/Traffic-Light-Controller-using-Verilog

    the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

    Language:JavaScript480015

  • mihir8181/VerilogHDL-Codes

    Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

    Language:Verilog40108

  • vedic-partap/Computer-Organization-and-Architecture-LAB

    Solution to COA LAB Assgn, IIT Kharagpur

    Language:Verilog36009

  • yigitbektasgursoy/SDRAM_Verilog

    Verilog HDL implementation of SDRAM controller and SDRAM model

    Language:Verilog32103

  • adibis/Interrupt_Controller

    An 8 input interrupt controller written in Verilog.

    Language:Verilog27309

  • coole198669/viterbi_decoder

    Hardware Viterbi Decoder in verilog

    Language:Verilog27113

  • sarthak268/Embedded_Logic_and_Design

    This repository contains all labs done as a part of the Embedded Logic and Design course.

    26102

  • ultraembedded/minispartan6-audio

    miniSpartan6+ (Spartan6) FPGA based MP3 Player

    Language:Verilog26229

  • lorentsinani/16bitCPU-Verilog

    16 bit CPU created in Vivado with Verilog

    Language:Verilog21103

  • Test134n/32-Verilog-Mini-Projects

    Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

    Language:Verilog20172

  • pendkeomkar/SPI

    Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

    19204

  • daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

    Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

    Language:Verilog17202

  • NikhilMukraj/spiking-neural-networks-hardware

    An FPGA design for simulating biological neurons

    Language:SystemVerilog17210

  • RPG-7/HGA101_GPU

    Language:Verilog17508

  • mnmhdanas/DA-Based-LMS-Adaptive-filter

    Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

    Language:Verilog16143
  • FliPGA01

    pescetti-studio/FliPGA01

    FPGA (Verilog) implementation of the Flip01 8-bit processor.

    Language:HTML16101

  • tongplw/Undertale-Verilog

    👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

    Language:Verilog15100

  • mnmhdanas/Router-1-x-3-

    Router 1 x 3 verilog implementation

    Language:Verilog14104

  • flasonil/Serial-Multiplier

    16 bit serial multiplier in SystemVerilog

    Language:SystemVerilog13015
  • my_rtl_code

    Nidhinchandran47/my_rtl_code

    Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

    Language:Verilog13111

  • cw1997/SDRAM-Controller

    SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

    Language:HTML12202

  • emrealci/FPGA-Verilog

    Practices related to the fundamental level of the programming language Verilog.

    Language:Verilog12102

  • vasanthkumar18/Cache-Compression

    Cache compression using BASE-DELTA-IMMEDIATE process in verilog

    Language:Verilog12218

  • yigitbektasgursoy/Motion_Estimation_Hardware_Verilog

    Motion Estimation implementation by using Verilog HDL

    Language:Verilog12101