/Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

Primary LanguageVerilog

Single-Cycle-Risc-Processor-32-bit-Verilog

Trying to implement a single cycle MIPS computer in Verilog that supports MIPS assembly instructions including:

  • Memory-reference instructions load word lw and store word sw
  • Arithmetic-logical instructions add, addi, sub, and, andi, or, and slt
  • Jumping instructions branch-equal beq and jump j

Below image is the Risc processor I am trying to impleent, But end product may not be exactly the same.
img_src: Click Here

RTL