risc
There are 265 repositories under risc topic.
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
LekKit/RVVM
The RISC-V Virtual Machine
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
michaeljclark/rv8
RISC-V simulator for x86-64
andrescv/jupiter
RISC-V Assembler and Runtime Simulator
MIPT-ILab/mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
Wren6991/RISCBoy
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
kvakil/venus
RISC-V instruction set simulator built for education
liuqdev/8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。
Mariotti94/WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
vmmc2/Vulcan
RISC-V Instruction Set Simulator (Built for education).
nikolaydubina/go-hackers-delight
"Hacker's Delight" in Go
mrisc32/mrisc32
MRSIC32 ISA documentation and development
AluVM/rust-aluvm
Rust implementation of AluVM (RISC functional machine)
edson-acordi/4bit-microcomputer
MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.
lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
openid/sharedsignals
OpenID Shared Signals Working Group Repository
fzipp/oberon
Project Oberon RISC emulator in Go
ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
SuperJMN/Plotty
C language compiler from scratch for a custom architecture, with virtual machine and all
michaeljclark/riscv-meta
RISC-V Instruction Set Metadata
ustb-owl/Uranus
Uranus MIPS processor by MaxXing & USTB NSCSCC team
wel97459/FPGACosmacELF
A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
schorrm/arm2riscv
Arm AArch64 to RISC-V Transpiler
sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog
Single Cycle RISC MIPS Processor
bitmario/RISVM
A low overhead, embeddable bytecode virtual machine in C++
platformio/platform-shakti
Shakti: development platform for PlatformIO
michahoiting/rv-link
RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).
spider-tronix/VLSI
RISC V core implementation using Verilog.
mrisc32/mrisc32-a1
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
pmetras/nim0
Nim0 is a toy compiler for a limited subset of Nim language, all in 5 heavily documented source files so that you can understand them. It is a port of Niklaus Wirth's Oberon-0 compiler.
orbit-systems/aphelion
64-bit RISC CPU Architecture
teivah/ettore
A RISC-V virtual processor, written in Rust.
lite-david/comet
RISC-V ISA based 32-bit processor written in HLS
SoCXin/TLSR8258
L1 R1: Telink 48MHz BLE SoC (TLSR8258/TLSR8253/TLSR8251)
ulx3s/ulx3s.github.io
community projects that can be used with the ULX3S FPGA ESP32 board