risc-processor
There are 83 repositories under risc-processor topic.
mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
mrLSD/riscv-fs
F# RISC-V Instruction Set formal specification
ash-olakangal/RISC-V-Processor
Verilog implementation of multi-stage 32-bit RISC-V processor
maikmerten/spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
suyashmahar/RISC-processor
Simple single cycle RISC processor written in Verilog
wyvernSemi/riscV
Open source ISS and logic RISC-V 32 bit project
sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog
Single Cycle RISC MIPS Processor
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
danielkasza/9444
9444 RISC-V 64IMA CPU and related tools and peripherals.
teivah/ettore
A RISC-V virtual processor, written in Rust.
djzenma/RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
sudhamshu091/Single-Cycle-Risc-Pipelined-Processor-Verilog
Single Cycle MIPS Pipelined Processor using Verilog
NayanaBannur/8-bit-RISC-Processor
A Verilog RTL model of a simple 8-bit RISC processor
ic-lab-duth/DRIM4HLS
DUTH RISC V Microprocessor for High Level Synthesis
barrettotte/Subarashii-CPU
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
thenamangoyal/RISC-Simulator
A C++ pipeline based simulator of RSIC architecture.
wannabeOG/CSN-221-Project
Implementation of a 24 bit RISC processor
Andrew-Hany/FemtoRV32-Piplined-Processor
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
emmapaczkowski/ELEC374
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
franout/DLX_project
Deluxe RISC processor
jofrfu/HAW-V
Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
meetdoshi90/8-Bit-RISC-Microprocessor
An 8-bit RISC based processor designed in verilog with x86 instructions.
mrLSD/riscv-cpu
RISC-V five stage pipline CPU
parshwa1999/NTP-Microprocessor
A real time Microprocessor impemented in verilog and tested on Xilinx Artix FPGA.
hcyang99/rv32-core
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
Luca-Dalmasso/DLX
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
Fiser12/Procesador-Segmentado
Procesador RISC segmentado creado con Proteus con Unidad de control, 5 segmentos, corrección de errores mediante unidad de detección de conflictos (DC) y ALU.
xerpi/sisa-emu
SISA Architecture Emulator
Alikberov/Koyaanisqatsi
Just bytes «B1 BC 2A C3 CB 4E» as «B₁ B,C ₂Add; C₃ C,B ₄Eor» is «Add B₁,C₂; Eor C₃,B₄» immediate with TTL-Circuit with 2 ticks per operation…
evgenabramov/MIPT-Compilers
🔧 MiniJava language compiler written in C++
Gluncho/Assembly-Emulator
This is an assembly emulator written in C++ language.
NaniteFactory/Elevator-with-Atmega128
A small elevator control system that runs on ATMEL's 8-bit microcontroller.
takatz28/RISCY-Processor
Final project for the class "Digital Design with Verilog and SystemVerilog"
TamaGo-HQ/cave_cpu
a primitive cavecpu for primitive cavemen