barrettotte/Subarashii-CPU
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
VerilogMIT
Issues
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Breadboard implementation of ALU
#27 opened by barrettotte - 0
ALU ADD/SUB operations (breadboard)
#28 opened by barrettotte - 0
Phase 2 planning and design
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Make an emulator in Python or C++
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VHDL implementation of ALU
#26 opened by barrettotte - 0
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Make register bank (VHDL)
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Finish phase 1 VHDL implementation
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Test register bank (breadboard)
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Implement Rd selector (breadboard)
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LEDs for registers and register selectors
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Test all phase 1 VHDL
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Implement Rs selector (breadboard)
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Replace registers with new compact design
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Rewrite VHDL implementation in terms of IC's
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Make last four 8-bit registers (breadboard)
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Design ALU
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Make four 8-bit registers (breadboard)
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Design RISC instruction set
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Begin documentation and design ISA
#8 opened by barrettotte - 0
Implement an 8-bit register (breadboard)
#7 opened by barrettotte - 0
Plan out phase 1 goals
#6 opened by barrettotte - 0
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Make register bank (breadboard)
#1 opened by barrettotte