vlsi-circuits
There are 48 repositories under vlsi-circuits topic.
OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
purdue-onchip/gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
OpenTimer/Parser-Verilog
A Standalone Structural Verilog Parser
luckyrantanplan/nthu-route
VLSI EDA Global Router
ehw-fit/evoapproxlib
Library of approximate arithmetic circuits
OpenTimer/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
imsanjoykb/Electrical-And-Electronic-Engineering-Course-Materials
Electrical And Electronic Engineering Course Materials
mihir8181/VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
srohit0/mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
SubZer0811/VLSI
All the projects and assignments done as part of VLSI course.
levibyte/pyqt_genetic_algo
genetic algorithm usage for routing optimization ( pyqt )
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
ali-ece/Design-of-optimal-CMOS-ring-oscillator-using-an-intelligent-optimization-tool
This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect tradeoff between the contradictory objective functions in CMOS RO optimal design. This tool is applied for intelligent estimation of the circuit parameters (channel width of transistors), which have a decisive influence on RO specifications. Along the optimal RO design in an specified range of oscillaton frequency, the Power Consumption, Phase Noise, Figure of Merit (FoM), Integration Index, Design Cycle Time are considered as objective functions. Also, in generation of Pareto front some important issues, i.e. Overall Nondominated Vector Generation (ONVG), and Spacing (S) are considered for more effectiveness of the obtained feasible solutions in application. Four optimization algorithms called Multi-Objective Genetic Algorithm (MOGA), Multi-Objective Inclined Planes system Optimization (MOIPO), Multi-Objective Particle Swarm Optimization (MOPSO) and Multi-Objective Modified Inclined Planes System Optimization (MOMIPO) are utilized for 0.18-mm CMOS technology with supply voltage of 1-V. Baesd on our extensive simulations and experimental results MOMIPO outperforms the best performance among other multi-objective algorithms in presented RO designing tool.
tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
trojanink/vlsi-cmos-inverter-design-magic
VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic
SalomeDevkule7/Carry-Select-Adder-8-bit
VLSI Physical Design
HsuChiChen/ncku-vlsi-circuit-design
delay estimation, sequencing, power dissipation of digital circuits
Gregory-Matthews/Dependable-Computing
Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.
RarityBrown/blog
Some ramblings about my major. 一些有关我的专业的碎碎念
RithikNambiar/vim_dotfiles
Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
Saadia-Hassan/Simulation-of-Memristor-Based-Full-Adder
LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.
FarshidKeivanian/Optimum-Layout-of-Multiplexer-with-Minimal-Average-Power-based-on-IWO-Fuzzy-IWO-GA-and-Fuzzy-GA
FuzzyIWO-Algorithm (Adaptive fuzzy optimisation algorithm)
PrashanthHC16/Approximate-Multipliers
Approximate multipliers of 8bit and 16bit
sujoyyyy/VLSI
Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.
AbhijnanPrakash/Passcode-Security-System
The main objective of this project is to provide a pass code based security system having the provision to change the pass code by the authority only, using XOR Gates as bit comparators and NOR Gates as controlled inverters. This proposed system will provide a user friendly security system for organizations and homes. If the pass code entered is right, it is indicated by a LED. Any wrong attempt to open the door (by entering the wrong password), an alert will be actuated, indicated by another LED.
AmrMEid/Digital-Design-Recap
A simple Recap for different Digital Design topics from different references and books.
FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
LijinWilson/CMOS-NAND-gate-2-input-NAND-gate
This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
manish2202/IEEE-paper-on-Automated-Car-Speed-Controller
Automated Car Speed Controller paperwork
santoshgs/AMRBot
VLSI sketches & Arduino Code for the Android-controlled Multiple Hazard Detection, Path Retracing, and Rescue Robot, or AMRBot.