wishbone
There are 51 repositories under wishbone topic.
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
ZipCPU/wb2axip
Bus bridges and other odds and ends
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
ZipCPU/autofpga
A utility for Composing FPGA designs from Peripherals
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
ZipCPU/openarty
An Open Source configuration of the Arty platform
jakubcabal/uart-for-fpga
Simple UART controller for FPGA written in VHDL
ZipCPU/wbscope
A wishbone controlled scope for FPGA's
lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
ZipCPU/s6soc
CMod-S6 SoC
ZipCPU/dbgbus
A collection of debugging busses developed and presented at zipcpu.com
stnolting/wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
ZipCPU/wbfmtx
A wishbone controlled FM transmitter hack
BLangOS/VexRiscV_with_HW-GDB_Server
VexRiscV system with GDB-Server in Hardware
lingbai-kong/computer-system
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
hotwolf/WbXbc
HDL components to build a customized Wishbone crossbar switch
merledu/caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
PacoReinaCampo/MPSoC-DMA
Direct Access Memory for MPSoC
pbing/ibex_wb
RISC-V Ibex core with Wishbone B4 interface
semahawk/wishbone
Trying to learn Wishbone by implementing few master/slave devices
ZipCPU/wbicapetwo
Wishbone to ICAPE interface conversion
bnossum/midgetv
rv32i/rv32im/rv32imc for iCE40. Wishbone interface.
rschlaikjer/fpga-3-softcores
Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
jracevedob/Processor-Design
In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.
PacoReinaCampo/MPSoC-UART
Universal Asynchronous Receiver-Transmitter for MPSoC
panda5mt/qf_wbfpga_pio
QuickLogic EOS S3:Cortex-M4 to FPGA Fabric via WISHBONE bus Sample Code with 8bit CAMERA-IF
semahawk/icarium
Trying to implement a soft core SoC
PacoReinaCampo/MPSoC-GPIO
General Purpose Input Output for MPSoC
PacoReinaCampo/MPSoC-MPI
Message Passing Interface for MPSoC
PacoReinaCampo/MPSoC-MPRAM
Multi-Port RAM for Instruction & Data for MPSoC
PacoReinaCampo/MPSoC-SPRAM
Single-Port RAM for Instruction & Data for MPSoC
pbing/J1_WB
Forth CPU J1 in SystemVerilog and Wishbone interface
batuhanates/ibex_wb
RISC-V Ibex core with Wishbone B4 interface
cyber-murmel/nmigen-wishbone-examples
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
PacoReinaCampo/MPSoC-MSI
Master Slave Interface for MPSoC