Icarium is meant to be a very simple, 64-bit RISC SoC, focusing on good debug-ability, sticking with KISS, and being nice to micro-kernels.
This project is in it's very very early stages, but I'm trying to document everything on the go here (a PDF version should also be available here).
I'm implementing Icarium in Verilog, using Xilinx ISE WebPack 14.7 as the SDK, XST as the sythesis tool, ISim as the simulation tool, Visual Studio Code as the main editor, Mimas V2 from Numato Labs featuring a Spartan 6 as the main real-life target board, and MimasV2Config.py as the tool to actually flash the board with.
Here's what I would love to have implemented at some point (in a somewhat ascending priority / hypeness):
- UART controller
- SPI controller
- I2C controller
- Interrupt controller
- cache (one shared stored in the intercon, and at least one in the CPU itself)
- DDR controller
- JTAG TAP controller
Because I can!
Well.. we'll see about that. This project is mainly meant just for me to understand how computers work under the hood.
Icarium was a mixed-blood Jaghut, a Jhag.[2] He was known under many names: Lifestealer,[3] the maker of machines, the chaser of time, lord of the sand grains.[4] Fiddler recalled the legend of "a Jaghut-blood wanderer around whom swirled, like the blackest wake, rumours of devastation, appalling murders, genocide".[5]
His constant companion was Mappo Runt the Trell.