xilinx-vitis
There are 13 repositories under xilinx-vitis topic.
triSYCL/sycl
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
nodamushi/vivado_cmake_module
CMake for Xilinx Vivado/Vitis
TurakhiaLab/DP-HLS
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
Xilover/Heterogeneous-Computing
Comprehensive open-source curriculum for mastering heterogeneous computing architectures and optimization.
aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Prithvish04/reconfigurable_project
Canny edge detection in HLS
ArioKian/Xilinx-Zynq7000-ZynqUltraScalePlus-PS-SdCard-Drivers
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
aryan-programmer/axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
efetunca/Zynq-7000-TFTP-Server
A TFTP server running on Zynq-7000
FrankKesel/xilinx_tools
Xilinx Tools Tutorials
justin-marian/cla-16bits-adder
Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.
harshonyou/TSP-on-FPGA
FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.
dennisleexyz/vitis-2019.2
:bookmark: Downgrade to 2019.2