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see nodamushi/vivado_init_project
- HLS sample: src/hls/hlsled/CMakeLists.txt
- Vivado sample: vivado/CMakeLists.txt
# set vivado version
set(VIVADO_REQUIRED_VERSION 2021.1)
# ------ Download -----------------------
include(FetchContent)
FetchContent_Declare(
vivado_cmake_module
GIT_REPOSITORY https://github.com/nodamushi/vivado_cmake_module.git
GIT_TAG v0.0.12
)
FetchContent_MakeAvailable(vivado_cmake_module)
list(APPEND CMAKE_MODULE_PATH ${vivado_cmake_module_SOURCE_DIR})
# -------- find package ------------------
find_package(Vivado)
find_package(HLS)
find_package(Vitis)
# ---- define Vivado project ------------
add_vivado_project(my_vivado_prj
TOP top_module
BOARD target_board
RTL top_module.v sub_module.v
CONSTRAINT cons.xdc
DESIGN design_1.tcl
)
# -- define vitis/vivado HLS project ---
add_hls_project(my_led
TOP HlsLED
PART target_part
VERSION 1.0
VENDOR nodamushi
NAME "LED"
PERIOD 10 # 100MHz
SOURCES hlsled.cpp
# Test bench
TB_SOURCES tb.cpp
)
# --- define vitis application project ---
add_vitis_hw_project(
my_vitis_prj
C # Not C++
XSA my_vivado_prj
PROC ps7_cortexa9_0
SOURCES src
)
mkdir build
cd build
cmake \
-DVIVADO_ROOT=/tools/Xilinx/Vivado/2022.2 \
-DVITIS_HLS_ROOT=/tools/Xilinx/Vitis_HLS/2022.2 \
..
# build hls project
make csynth_my_led
# build vivado project
make impl_my_vivado_prj
find_package(Vivado)
VIVADO_ROOT
: option. Vivado hls root path. exp)cmake -DVIVADO_HLS_ROOT=/tools/Xilinx/Vivado/2019.2
XILINX_VIVADO
: Environment variable defined bysource <path to Vivado>/settings64.sh
.
VIVADO_JOB
: option. implement job size
VIVADO_VERSION
: Vitis/Vivado HLS versionVIVADO_EXE
: vivado command pathVIVADO_XSDB_VIVADO
: xsdb command path
add_vivado_project
add_vivado_project(
<project>
BOARD <board part name>
TOP <top module>
[DIR <directory name>]
[RTL <file/directory>...]
[CONSTRAINT <file/directory>...]
[IP <directory>...]
[DESIGN <tcl file>]
[DEPENDS <target>...]
[TCL0 <tcl file>...]
[TCL1 <tcl file>...]
[TCL2 <tcl file>...]
[DFX <tcl file>]
[IMPLEMENTS <implimentation name>...]
[BOARD_REPO <directory>...]
[BETA <beta device pattern>]
[PDI]
)
<project>
: target name
BOARD
: Board property. When*
is contained, find board part by Vivado command[get_board_parts -quiet -latest_file_version <BOARD>]
.TOP
: Top module name
DIR
: project directory name (default isprojet
.prj)RTL
: RTL filesCONSTRAINT
: constraint filesIP
: IP directoriesDESIGN
: Design tcl fileDEPENDS
: dependsTCL0
: Tcl script files. This file will be loaded beforecreate_project
command.TCL1
: Tcl script files. This file will be loaded after adding RTL/constraints files increate_vivado_project.tcl
.TCL2
: Tcl script files. This file will be loaded before closeing project increate_vivado_project.tcl
.DFX
: Enable Dynamic Function eXchange(Partial Reconfigu), and load setting tcl file.IMPLEMENTS
: impelmentation name listBOARD_REPO
: set_param board.repoPathsBETA
: enable_beta_device command arguments.*
is all beta device enable.PDI
: for Versal. Indicates that Vivado generates *.pdi files.
Note: <project>
is the first argument of add_vivado_projct
.
<project>
: Create Vivado project- Target Properties
PROJECT_NAME
: project namePROJECT_DIR
: project directory pathPROJECT_FILE
: xpr file pathRUNS_DIR
: .runs directory pathIMPL
: default implementation nameIMPLS
: implementation listTOP_MODULE
: top module nameTOP_BITSTREAM
: top bit stream pathTOP_LTX
: top bit stream ltx pathIMPL_TARGET
: implementation target name :
- Target Properties
open_<project>
: Open project in vivadoclear_<project>
: Delete Vivado project directoryimpl_<project>
: Create bit stream (run impl)program_<project>
: Write bitstream- Environment Variables:
JTAG
: jtag targetHWSVR
: (option)hw_server
urlHWSVRPORT
: (option)hw_server
port
- exp)
make JTAG=1 program_<project>
- Environment Variables:
export_bd_<project>
: Save IP Integrator design tcl filereport_addr_<project>
: Report address- Environment Variables:
REPORT_CSV
: output csv file name
- exp)
make REPORT_CSV=foobar.csv report_addr_<project>
- Environment Variables:
Add new target to write bitstream of project.
add_write_bitstream(project target_subname bitstream_path)
project
: target projecttarget_subname
: write bitstream target namebitstream_path
: bitstream file path from project runs directory
program_<project>_<target_subname>
- Environment Variables:
JTAG
: jtag targetHWSVR
: (option) connect urlHWSVRPORT
: (option) connect port
- exp) make JTAG=1 program_${project}_${target_subname}
- Environment Variables:
find_package(HLS)
VITIS_HLS_ROOT
: option. Vitis hls root path. exp)cmake -DVITIS_HLS_ROOT=/tools/Xilinx/Vitis_HLS/2022.2
XILINX_HLS
: Environment variable defined bysource <path to Vitis HLS>/settings64.sh
.
VIVADO_ROOT
: option. Vivado hls root path. exp)cmake -DVIVADO_HLS_ROOT=/tools/Xilinx/Vivado/2019.2
XILINX_VIVADO
: Environment variable defined bysource <path to Vivado>/settings64.sh
.
HLS_VENDOR_NAME
: option. Default IP vendor name.HLS_TAXONOMY
: option. Default IP category name.HLS_DEFAULT_VERSION
: option. Default IP VersionVITIS_HLS_FLOW_TARGET
: option. Default Vitis HLS flow target.
HLS_VERSION
: Vitis/Vivado HLS versionHLS_IS_VITIS
: whether Vitis HLS is detectedHLS_IS_VIVADO
: whether Vivado HLS is detectedHLS_BIN_DIR
:bin
directory path of Vitis/Vivado HLSHLS_INCLUDE_DIR
:include
directory path of Vitis/Vivado HLS
add_hls_project(
<project>
TOP <top module>
PERIOD <clock period(ns)>
PART <board part>
SOURCES <C++ source file>...
[INCDIRS <include directory>...]
[LINK <link library>...]
[TB_SOURCES <test bench C++ file>...]
[TB_INCDIRS <include directory>...]
[TB_LINK <link libray>...]
[DEPENDS <depends target>...]
[NAME <display name>]
[IPNAME <IP name>]
[VENDOR <your name>]
[TAXONOMY <category>]
[VERSION <version(x.y)>]
[SOLUTION <solution name>]
[COSIM_LDFLAGS <flag string>]
[COSIM_TRACE_LEVEL <none|all|port|port_hier>]
[FLOW_TARGET <vivado|vitis>]
[CFLAG <flags>...]
[TB_CFLAG <flags>...]
[DEFINE <macro[=value]>...]
[TB_DEFINE <macro[=value]>...]
[CTEST]
[NO_O0]
)
sample code
add_hls_project(
hlsled # project name
# Project info
TOP HlsLED # top module function name
VERSION 1.0 # IP version
VENDOR "foobar" # vendor name
NAME "HLS LED Chika" # display name
PERIOD 10 # clock period[ns] (10 = 100MHz)
PART xc7z007sclg400-1 # fpga part
# source
SOURCES hlsled.cpp # source file list
LINK my_hls_lib # add library. see `add_hls_interface`
# test
TB_SOURCES tb.cpp # test bench file list
TB_LINK my_test_lib # add library. see `add_hls_interface`
CTEST # add_test(NAME test_hlsled COMMAND $<TARGET_FILE:build_test_hlsled>)
)
<project>
: target name
TOP
: Top module namePERIOD
: Clock Period (ns)PART
: Device partSOURCES
: HLS source file
NAME
: IP display name. (Default is<project>
)IPNAME
: IP name.(Default is<project>
)VENDOR
: Your name.(Default isHLS_VENDOR_NAME
variable)TAXONOMY
: IP category.(Default isHLS_TAXONOMY
variable)VERSION
: IP version(x.y).(Default isHLS_DEFAULT_VERSION
variable)SOLUTION
: Solution name.(Default isHLS_SOLUTION_NAME
variable)TB_SOURCES
: Test Bench source filesINCDIRS
: Include directoriesTB_INCDIRS
: Include directories for test benchDEPENDS
: Dependency for create projectLINK
: Link libraryTB_LINK
: Link library for testingCOSIM_LDFLAGS
: cosim_design -ldflagsCOSIM_TRACE_LEVEL
: default none, all, port, port_hier. (Default isHLS_TRACE_LEVEL
variable)FLOW_TARGET
: (vitis_hls only). vivado or vitis.(Default isVITIS_HLS_FLOW_TARGET
variable)CFLAG
: Additional compile flagTB_CFLAG
: Additional test bench compile flagDEFINE
: Define macroTB_DEFINE
: Define macro for test benchNO_O0
: Disable -O0 option oftest_<project>
target.CTEST
: calladd_test
.
Note: <project>
is the first argument of add_hls_projct
.
create_project_<project>
: Create Vitis Projectclear_<project>
: Delete Vitis project directorycsynth_<project>
: Run synthesislib_<project>
: Compile C++test_<project>
: Compile TestBenchwave_<project>
: Open cosim wave database in Vivadocosim_<project>
: C/RTL simulationTLEVEL
: trace level.make TLEVEL=all cosim_<project>
ARGV
: arguments.make ARGV="-foo -bar" cosim_<project>
see: Vitis HLS 2021.x - Use of gmp.h for Co-simulation
By always including the following code at the beginning of the test code, this problem can be avoided.
#include <_gmp_const.h>
gmp_const.h
is gmp/gmp_const.h
or nogmp/gmp_const.h
.
add_hls_interface(
project
[INCDIRS <directory>...]
[DEPENDS <target>...]
)
project
: interface library target name
INCDIRS
: header directories.If this option is not specified, the current directory is set.DEPENDS
: depends targets
<project>
: interface library target
find_package(Vitis)
add_vitis_hw_project(
<project>
XSA <vivado project|xsa file>
PROC <proecessor name>
[C|CPP]
[OS <os name>]
[DIR <workspace directory>]
[DOMAIN_NAME <domain short name>]
[DOMAIN_LONG <domain long name>]
[TEMPLATE <project tempalte name>]
[SOURCES <source file|directory>...]
[DEPENDS <denpend target>...]
[INCDIR <include directory>...]
[DEFINE <macro>...]
[TCL0 <user tcl script>...]
[TCL1 <user tcl script>...]
[TCL2 <user tcl script>...]
[TCL3 <user tcl script>...]
[ARCH microblaze|aarch64|aarch32|armr5]
)
sample code:
# * source vivado project *
add_vivado_project(
sample_vivado
DESIGN top.tcl
TOP top_wrapper
BOARD <your target board>
)
##########################
## Sample Vitis project ##
##########################
add_vitis_hw_project(
sample_vitis # project name
C # C language. (Default is C++)
XSA sample_vivado # source vivado project
PROC ps7_cortexa9_0 # processor name
SOURCES src # source directory
)
create_${project}
: Generate workspace / platform / application${projecte}
: Build projectclear_${project}
: Delete workspaceopen_${project}
: Open workspace in Vitisshow_proc_${project}
: Show processor list
create_${project}
fails, run clear_${project}
before trying again.
<project>
: project namePROC
: processor nameXSA
: vivado project or xsa file path
C|CPP
: Supported language. C => C language, CPP => C++ language. If this option is not defined,VITIS_DEFAULT_LANG
will be used.OS
: project os. default is standalone.DIR
: workspace directoryDOMAIN_NAME
: domain name.DOMAIN_LONG
: domain display name.TEMPLATE
: application project template name. If this option is not defined,VITIS_XXX_TEMPLATE
will be used.SOURCES
: source files or directoriesDEPENDS
: dependsINCDIR
: include directories.DEFINE
: macroTCL0,1,2,3
: user tcl scripts. seetcl/create_vitis_project.tcl
ARCH
: microblaze or aarch64 or aarch32 or armr5