xilinx-hls

There are 9 repositories under xilinx-hls topic.

  • cea-wind/hls_ldpc_dec

    Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..

    Language:C++415218

  • lastweek/fpga_icap_hls

    HLS-based Xilinx ICAP3 Controller (tested with VCU108)

    Language:Tcl1010

  • matthiaskonrath/rc4-verilog

    EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.

    Language:C++8100

  • nodamushi/vivado_cmake_module

    CMake for Xilinx Vivado/Vitis

    Language:CMake8111

  • aryan-programmer/axi_gen_and_sum_primes_fpga

    A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

    Language:TeX3200

  • aryan-programmer/axi_stream_array_sum_microblaze

    A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

    Language:C2201

  • wurmmi/fm-radio

    Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).

    Language:VHDL2100

  • harshonyou/TSP-on-FPGA

    FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

    Language:C0102

  • cescalara/zynq_ip_hls

    Custom IP for the Mini-EUSO PDM-DP Zynq system

    Language:C++10