Typo in uvm_reg_field.py

[sjalloq]

I've been starting to use my register model and have been confused at why I can't trigger an error on reg.mirror(). It looks like there's another typo in uvm_reg_field.py where the initial value of m_check is set to UVM_NO_CHECK instead of UVM_CHECK.

In the SV version, the configure method checks if the field is volatile or not and sets the check field appropriately:

   function void uvm_reg_field::configure(uvm_reg        parent,
                                          int unsigned   size,
                                          int unsigned   lsb_pos,
                                          string         access,
                                          bit            volatile,
                                          uvm_reg_data_t reset,
                                          bit            has_reset,
                                          bit            is_rand,
                                          bit            individually_accessible); 
      m_parent = parent;
      if (size == 0) begin
         `uvm_error("RegModel",
            $sformatf("Field \"%s\" cannot have 0 bits", get_full_name()));
         size = 1;
      end
   
      m_size      = size;
      m_volatile  = volatile;
      m_access    = access.toupper();
      m_lsb       = lsb_pos;
      m_cover_on  = UVM_NO_COVERAGE;
      m_written   = 0;
      m_check     = volatile ? UVM_NO_CHECK : UVM_CHECK;

In uvm_reg_field.py, the variable is set in the __init__() method to UVM_NO_CHECK and then in configure() method, if it's volatile, the same value is written. I think the initial value should be changed to:

   def __init__(self, name='uvm_reg_field'):
        """
        This method should not be used directly.
        The `UVMRegField.type_id.create()` factory method
        should be used instead.

        Args:
            name: (str): Name of the register field
        """
        UVMObject.__init__(self, name)
        self.value = 0  # Mirrored after randomize()
        self.m_mirrored = 0  # What we think is in the HW
        self.m_desired = 0  # Mirrored after set()
        self.m_access = ""
        self.m_parent = None  # uvm_reg
        self.m_lsb = 0
        self.m_size = 0
        self.m_volatile = False
        self.m_reset = {}  # string -> uvm_reg_data_t
        self.m_written = False
        self.m_read_in_progress = False
        self.m_write_in_progress = False
        self.m_fname = ""
        self.m_lineno = 0
        self.m_cover_on = 0
        self.m_individually_accessible = False
        self.m_check = UVM_CHECK  # uvm_check_e

and then the configure() method doesn't need to change (although removing the else case would be a positive):

   def configure(self, parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand,
            individually_accessible):
 # ...snip...
        if volatile:
            self.m_check = UVM_NO_CHECK
        else:
            self.m_check = self.m_check

[tpoikela]

else branch was most likely a typo on my part. It does not make sense to have it in the first place. Thanks for the PR and fix for this!

[sjalloq]

Closing as this fix has been merged now.