tpoikela/uvm-python

Issues

• How to generate file dumpwave by code uvm-python?

  #54 opened a month ago by AnhHonag
  0

• It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).

  #53 opened a month ago by 717-yq
  3

• how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?

  #52 opened 6 months ago by 717-yq
  2

• Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library?

  #48 opened 7 months ago by sbhutada
  1

• Any example that shows integrating C++/SystemC predictor?

  #49 opened 7 months ago by sbhutada
  1

• examples/sv is failing ... any ideas?

  #50 opened 9 months ago by sbhutada
  1

• Do you support uvm_component_param_utils? Any alternative approach? Any example?

  #51 opened 8 months ago by sbhutada
  3

• Is there a way to mix SystemVerilog UVM and UVM-Python environments?

  #47 opened 9 months ago by sbhutada
  2

• uvm_do doesn't work

  #45 opened 9 months ago by M0stafaRady
  2

• Using uvm-python for with custom build infrastructure

  #46 opened 9 months ago by sbhutada
  4

• uvm hw reset sequence bug

  #41 opened a year ago by SikoVerilog
  2

• Test failing

  #44 opened a year ago by psumesh
  1

• Cross TLM communication

  #40 opened 2 years ago by psumesh
  2

• registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT

  #26 opened 4 years ago by tpoikela
  11

• test uvm-python/test/examples/integrated/ubus/examples for "read modify write" can not be randomized with the uvm_do_with

  #39 opened 4 years ago by ogheri
  3

• Latest version of cocotb Verilator will always issue error %Error-TIMESCALEMOD.

  #37 opened 4 years ago by jg-fossh
  4

• Correct way to clean up UVM objects

  #36 opened 4 years ago by sjalloq
  2

• Typo in uvm_reg_field.py

  #34 opened 4 years ago by sjalloq
  2

• What is the correct way to update the mirrored state of a register?

  #28 opened 4 years ago by sjalloq
  7

• Bug in uvm_reg_map.py

  #32 opened 4 years ago by sjalloq
  3

• Documentation rendering issue

  #27 opened 4 years ago by sjalloq
  7

• UVM Python minimal test

  #22 opened 4 years ago by tsengr0916
  6

• uvm_info

  #21 opened 4 years ago by zfling
  6

• type error

  #15 opened 4 years ago by zfling
  11

• Failed to import module new_test: No module named 'uvm'

  #14 opened 5 years ago by zfling
  8