Pinned Repositories
7-segment
AUCOHL_TMR32
A 32-bit Timer and PWM generator.
AUCOHL_UART
A more complete UART
caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_board
caravel_cocotb_tests
test for caravel features
caravel_coverage_results
caravel_ips_tc
caravel_openframe_project
Example digital project for the Efabless Caravel "openframe" harness
RST_CLK_CTRL
M0stafaRady's Repositories
M0stafaRady/RST_CLK_CTRL
M0stafaRady/7-segment
M0stafaRady/AUCOHL_TMR32
A 32-bit Timer and PWM generator.
M0stafaRady/AUCOHL_UART
A more complete UART
M0stafaRady/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
M0stafaRady/caravel_board
M0stafaRady/caravel_cocotb_tests
test for caravel features
M0stafaRady/caravel_coverage_results
M0stafaRady/caravel_ips_tc
M0stafaRady/caravel_openframe_project
Example digital project for the Efabless Caravel "openframe" harness
M0stafaRady/mpc
Multi-Project Support for Caravel
M0stafaRady/MS_CLK_RST
All digital clock and rest controller
M0stafaRady/MS_DMAC_AHBL
fix typo in FSM
M0stafaRady/ahbl_dmac
Nano AHB Lite DMA Controller
M0stafaRady/docs
M0stafaRady/IP_Utilities
AUC Open Hardware Lab (AUCOHL) IP Utilities
M0stafaRady/ms_i2c
i2c master controller with an APB interface
M0stafaRady/ms_psram_ctrl
A Quad I/O SPI Pseudo Static RAM (PSRAM) Controller
M0stafaRady/MS_QSPI_XIP_CACHE
AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
M0stafaRady/ms_tmr32
A 32-bit Timer/Counter/Capture/PWM Soft IP (Verilog)
M0stafaRady/ms_uart
M0stafaRady/open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
M0stafaRady/seven_seg_gui
verify 7 segment design using cocotb and gui