Pinned Repositories
aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
aes-1
Fully pipelined AES module written in SystemVerilog. WIP.
aes-2
Hardware and software implementation of AES algorithm
aes-encryption
fast AES-128 Encryption only cores
aes_pipe
Pipelined AES
awesome-smartnic
A curated list of awesome smartnic tutorials, papers and projects.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
dpa-app
Tool to initialize and configure DPAA with classifier policies
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
FPGA-SM3-HASH
Description of Chinese SM3 Hash algorithm with Verilog HDL
tszhou1989's Repositories
tszhou1989/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
tszhou1989/aes-1
Fully pipelined AES module written in SystemVerilog. WIP.
tszhou1989/aes-2
Hardware and software implementation of AES algorithm
tszhou1989/aes-encryption
fast AES-128 Encryption only cores
tszhou1989/aes_pipe
Pipelined AES
tszhou1989/awesome-smartnic
A curated list of awesome smartnic tutorials, papers and projects.
tszhou1989/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
tszhou1989/dpa-app
Tool to initialize and configure DPAA with classifier policies
tszhou1989/fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
tszhou1989/FPGA-SM3-HASH
Description of Chinese SM3 Hash algorithm with Verilog HDL
tszhou1989/FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
tszhou1989/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
tszhou1989/HyperParser
tszhou1989/Low-Cost-and-Programmable-CRC
Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
tszhou1989/opentitan
OpenTitan: Open source silicon root of trust
tszhou1989/panic_osdi20_artifact
tszhou1989/perc-p4
Source files of the P4 & Verilog NetFPGA SUME implementation of the s-PERC switch
tszhou1989/SMx
国家商用加密算法 SMx（SM2,SM3,SM4）
tszhou1989/spc
Soft Parser Configuration tool
tszhou1989/System-Verilog-Packet-Library
System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
tszhou1989/trex-core
trex-core site