Pinned Repositories
Implementation-of-Simplified-TCP-using-the-NIOS-II-in-Intel-DE2i-150-FPGA-board.
Created Qsys system that includes Nios II, Triple-Speed Ethernet IP Core, SGDMA controller and other hardware components for transmit and receive operation. Two Phase-Locked Loop modules are added to the design to generate clocks with different frequencies to make the Triple-Speed Ethernet system (which implements the MAC function) work properly at 10/100/1000 Mbps. After building the hardware system and downloading the circuit onto the FPGA, run an application program written in C language. Based on the inputs from the board it establishes and closes the TCP connection, transmit and receive data frames from the Ethernet port of the board. Ethernet frames are transmitted based on Stop and Wait Protocol and Altera Timer core is added to re-transmit frames after Timeout.
introductory-guide-to-chisel
「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ
J1Sc
A reimplementation of a tiny stack CPU
tvm
My experiences of using TVM compiler on Raspberry Pi 3 Model B
ZYBO_IoT_Vivado
This is a Vivado project to create an IoT device with ZYBO (Zynq).
tzechienchu's Repositories
tzechienchu/tvm
My experiences of using TVM compiler on Raspberry Pi 3 Model B
tzechienchu/8051-tuner
3-octave tone generator using an 8051 MCU
tzechienchu/awesome-micropython-lib
Awesome MicroPython libs
tzechienchu/BNN-PYNQ
tzechienchu/Chisel-wavetable
synth stuff for fpga
tzechienchu/cv2PYNQ-The-project-behind-the-library
This project describes how the cv2PYNQ python library was built
tzechienchu/De10-Lite_HDL_GPS
Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine
tzechienchu/Deep-Neural-Network-Hardware-Accelerator
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
tzechienchu/e200_opensource
The Ultra-Low Power RISC Core
tzechienchu/esp32_mouse_keyboard
ESP32 implementation for HID over GATT Keyboard and Mouse (Bluetooth Low Energy). Including serial API for external modules (similar to Adafruit EZKey HID)
tzechienchu/HLx_Examples
Open Source HLx Examples
tzechienchu/homemade-riscv
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
tzechienchu/insightface
Face Recognition Project on MXNet
tzechienchu/Intro-Comp-Neuro
Codes to accompany the book An Introductory Course in Computational Neuroscience
tzechienchu/linux-in-practice
tzechienchu/Mersenne-Twister-HLS
High Level Synthesis (Xilinx HLS) implementation of the popular Mersenne Twister pseudo-random number generator. This will generate a VHDL/Verilog module that streams 32 bit psuedo-randoms at 500 MHz on a Virtex 7 FPGA.
tzechienchu/mxnet-ssd-tvm
tzechienchu/mxnet_Realtime_Multi-Person_Pose_Estimation
This is a mxnet version of Realtime_Multi-Person_Pose_Estimation, origin code is here https://github.com/ZheC/Realtime_Multi-Person_Pose_Estimation
tzechienchu/node-spi
A NodeJS interface to the SPI bus on embedded linux machines
tzechienchu/Pattern_Matching-fpga
Exact pattern matching in given DNA text using fpga
tzechienchu/perfect-chisel
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
tzechienchu/posenet-nodejs
🙆♂️ Pose tracking with TensorflowJS in Nodejs
tzechienchu/PYNQ
Python Productivity for ZYNQ
tzechienchu/pynq-ekf
A multi-board Extended Kalman Filter (EKF)
tzechienchu/PyTorch-for-Deep-Learning-and-Computer-Vision-Course-All-Codes-
PyTorch for Deep Learning and Computer Vision Course
tzechienchu/RISC-V-On-PYNQ
RISC-V Integration for PYNQ
tzechienchu/RPi-Bluetooth-Console
tzechienchu/SDSoC-Ultra96
Ultra96 SDSoC Platform created for SDx 2018.2, Vivado 2018.2, and PetaLinux 2018.2.
tzechienchu/STM32F407-DISCOVERY-rust
A boilerplate template for Rust on the STM32F407-DISCOVERY board.
tzechienchu/SuperSpeed-Design-Examples-V1.2
SuperSpeed Design Examples V1.2 From John Hyde's book (i.e. Superspeed Device Design by Example.)