ujansengupta/cache_simulator

A cache simulator which simulates the L1 and L2 cache for a single processor. Since this is a simulator, no actual data is stored. Also, the simulator takes in inputs such as the cache sizes, associativity and block sizes and maintains coherence across the two levels of caches. The output contains details about the number of cache hits, misses, writebacks (from L1 to L2 and L2 to the memory), etc.

C