Pinned Repositories
cs522_project
rip
common_cells
Common SV components
frizzle
A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems and computer architecture classroom use in mind.
jtag_vpi
TCP/IP controlled VPI JTAG Interface.
litax25
LiteX IP for AX.25 packet radio
MySpinClass
My Spin Class!!
riscv-dbg
RISC-V Debug Support for our PULP Cores
systemc
Core SystemC Library
wbuart32
A simple, basic, formally verified UART controller
umenthum's Repositories
umenthum/frizzle
A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems and computer architecture classroom use in mind.
umenthum/riscv-dbg
RISC-V Debug Support for our PULP Cores
umenthum/common_cells
Common SV components
umenthum/jtag_vpi
TCP/IP controlled VPI JTAG Interface.
umenthum/litax25
LiteX IP for AX.25 packet radio
umenthum/MySpinClass
My Spin Class!!
umenthum/systemc
Core SystemC Library
umenthum/wbuart32
A simple, basic, formally verified UART controller