KD240 PWM LED

This article mainly explains how to implement a breathing light effect on the KD240

Last update: 2024/05/18

Achieve with Vivado & Vitis Design Flow
Achieve with PYNQ Design Flow

Vivado

Custom PWM IP

Vivado has the option to create and package IP under the Tools menu in the top bar. The following section will demonstrate how to add a PWM IP to the IP Catalog for future use

Select Create and Package New IP in Vivado
Proceed with the default settings by clicking Next

Set up the PWM IP, which will open a temporary project to configure the IP

Add the PWM RTL code, Source Code - ax_pwm.v

Modify the AXI Top RTL code to incorporate the PWM RTL code

pwm_v1_0_S00_AXI.v

pwm_v1_0.v

Ensure that the AXI Reset is set to 0 as the initial register value, consistent with the PWM Code

Merge Changes and Re-Package IP

Create Block Design - Start by importing IP into the Block Diagram in Vivado using the GUI

Call ZYNQ IP

Call PWM IP

Define the PWM IP output ports as external interfaces

Automatically connect the IP via the AXI Bus using Vivado's Connection Automation

Validate the design to ensure there are no issues

Add XDC content

XDC content can be cross-referenced with the KD240 circuit diagram

Generate Bitstream - Generate the programming file and export hardware information to Vitis

Generate Bitstream, processing time varies depending on computer performance

Export Hardware, which generates a .xsa file for Vitis Import

Modify the XSA content for custom IP by opening the Makefile through winrar

Modify the following content and save

Vitis

Create Platform and Application

Create Platform

After creating, build first to have Library linkage files

Create Application

Select the newly created Platform

Proceed with Next until selecting Hello World as the program template

Modify KD240 BSP - because the default Kria Uart is set to 1, but in Vitis it is set to 0

The other two files also need to be changed to the above format

Remember to rebuild after modifying

Open helloworld.c and modify the program content as follows

Modify KD240 Boot Behavior

Because the Kria series defaults to booting from QSPI, followed by SD card, direct burning may have Register jamming issues, which can be resolved in two ways
Modify KD240 boot mode

Modify the boot mode through TCL Setting Bootmodes — Kria™ SOM 2022.1 documentation (xilinx.github.io)

After creating the TCL file, enter the following in the xsct of Vitis

connect
source ./bootmode.tcl ---> cd to the location where you put the TCL file
boot_jtag

Modify Run Configuration

Uncheck Use FSBL flow for initialization

Program and Run Demo

The program is successful

PYNQ

This section explains how to control IP written in RTL code in Vivado using Python
Functions to control IP in Python need to refer to Vitis
Adding flashing LEDs on the PL Ethernet port requires pulling GPIO LEDs again from Vivado

Burn the official Ubuntu Image to the KD240, following the steps in the KD240 BIST section

Download Ubuntu 22.04 and put it in SDcard through balenaetcher
Boot Ubuntu 22.04 from KD240
sudo add-apt-repository ppa:xilinx-apps (Optional)
Update Ubuntu package

sudo apt update
sudo apt upgrade

Install Xilinx system management snap package ---> sudo snap install xlnx-config --classic (Optional)
Install Kria-PYNQ

git clone https://github.com/Xilinx/Kria-PYNQ.git
cd Kria-PYNQ
sudo bash install.sh -b KD240

After successful installation, open a browser on the same network and enter the provided URL to access Jupyter Lab

Create a folder named PWM_LED

Navigate into the PWM_LED folder and place the generated .bit and .hwh files from Vivado. Then create a new Python file

The .hwh file is located in the Vivado .gen\sources_1\bd\design_1\hw_handoff directory

Start writing Python code in the Python file. The following describes the coding process and API usage. First, import the required Python and PYNQ library packages

from pynq import Overlay     ---> The overlay is used for loading bitstream
from pynq.lib import AxiGPIO ---> AxiGPIO is used for reading and writing registers in IP blocks with GPIO
import time                  ---> Time is used for delay time control
from pynq import MMIO        ---> MMIO is used for reading and writing registers in PL by PS. In this case, it's used to control the PL PWM IP
import multiprocessing as mp ---> Multiprocessing allows executing multiple loops simultaneously

Load the bitstream using Overlay. Note that both the .bit and .hwh files are required

Use help(overlay) to view the IP used in the current .bit file, its architecture, and how it corresponds to the design in Vivado

Initialize the IP

Because there are two sets of LEDs on the KD240 PL Ethernet, an additional channel must be set (this step is also required when there is only one set of LEDs)

Set the GPIO direction, i.e., mask. 0x0 is input, 0xf is output. Also, set the delay value for LED blinking (in seconds)

Write the function for LED lighting on the Ethernet port

LED values for PL Ethernet:
0: Right LED on
1: All LEDs off
2: All LEDs on
3: Left LED on

Set the memory and register values for the PWM IP

These points can refer to Vitis and the Address Editor in Vivado

Write the PWM IP function. MMIO reads and writes values to memory locations, similar to the logic in Vitis. You can adapt the Vitis C code to Python code

To execute both loops simultaneously, use Multi-Process to add the functions to different processes and run them synchronously

Demo result

vaan2010/KD240-Breath-LED

KD240 PWM LED

Vivado

Custom PWM IP

Create Block Design - Start by importing IP into the Block Diagram in Vivado using the GUI

Generate Bitstream - Generate the programming file and export hardware information to Vitis

Vitis

Create Platform and Application

Modify KD240 Boot Behavior

Program and Run Demo

PYNQ

Reference