/ZC702-Test-Pattern-Generator-Flow

ZC702 Test Pattern Generator Flow

  • This article covers generating test pattern generator images through ADV7511 HDMI, including resolution conversion functionality, for ZC702

Last update: 2024/05/18

Build ZC702 Block Design on Vivado

1. Create Block Design and perform IP design

  • ZYNQ7 Processing System

  • Video Test Pattern Generator

  • AXI4-Stream to Video Out

  • Video Timing Controller

  • Clocking Wizard

148.5 𝑀ℎ𝑧=(2200×1125×60)/10^6

  • AXI IIC

  • Begin connecting the above IPs to start the integration process

Data width inconsistency

We solve it by adding an AXI-4 Stream Subset Converter

2. Add constraints detailing how HDMI is connected to the ADV7511's pins. You can download the zip file from this directory and locate the XDC file at XVES_0019\src\constr\ZC702.xdc

  • Modify the constraints to match the port naming in the Block Design

3. Create HDL Wrapper & Generate Bitstream

4. Export Hardware，This step will output XSA to Vitis for writing C code to control the FPGA

Build ZC702 Application on Vitis

5. Open Vitis, import the XSA, and create a platform

  • After creating the platform, proceed to build it to generate the linkage files

6. Create an application and import the files from the "src" folder in the zip file

7. Delete the original helloworld.c, then open tpg_hdmi_zc702.c and add the code highlighted in the diagram below

8. ZC702 Hardware Configuration

9. Right-click on Application and select Run as 1 Launch Hardware to view the results

ZC702 Test Pattern Generator Output Multiple Resolution Flow

Modify IP on Vivado

1. Make adjustments to IP configurations in the aforementioned Block Design

  • Video Timing Controller - Enable AXI-4 Lite for control by C code in Vitis

  • Clocking Wizard

Enable Dynamic Reconfiguration to update clocks from AXI-4 Lite through Vitis

Check the desired clock values corresponding to different resolutions for output

25.2 𝑀ℎ𝑧=480𝑃

74.25 𝑀ℎ𝑧=720𝑃

148.5 𝑀ℎ𝑧=1080𝑃

Enable MMCM Override

Remember the following division values, which will be used by Vitis

Go back and deselect the other two output clocks. Remember to modify the corresponding resolutions in the VTC

  • Connect the above IPs together

2. Generate the bitstream as before and export the XSA

Build ZC702 Application on Vitis

3. Update the previously created platform by importing the new XSA, and rebuild it as before

4. Create the application, import the previously modified code, and make further changes in tpg_hdmi_zc702.c as follows:

If not changing the resolution, comment out the two lines in the Clocking Wizard Configuration

If not changing the resolution, comment out the three lines in the VTC Configuration

Note that simply not changing the original resolution or clock speed does not require reconfiguration, but if there is an AXI-4 Lite, you need to initialize and enable that IP in Vitis for it to function

5. Run as 1 Launch Hardware，Check the results

  • 480P

  • 720P

  • 1080P

Reference