vctrop
CpE interested in signal processing, microelectronics, computer intelligence and electrophysiology.
Centro Espacial ITA (CEI)Brazil
Pinned Repositories
AMBA_playground
Design and experimentation with nodes using the AMBA protocol
article_manager
A toy project to help organizing conference and journal scientific articles
bank_of_metaheuristics
Implementation of multiple metaheuristics.
cei_apb3uart
Description of a memory-mapped UART controller using the AMBA 3 APB bus protocol
image_histogram_data_hiding
Image steganography for data hiding using the histogram-based technique developed by Ni et al., 2006.
laguerre-volterra_network
Implementation of Laguerre-Volterra networks and different methodologies for their optimization, aiming nonlinear dynamic sys. identification
metaheuristics_for_Laguerre-Volterra_networks_optimization
Optimization of Laguerre-Volterra networks for nonlinear dynamic system identification using diverse metaheuristics
overlap_save_convolution
Implementation of the overlap-save algorithm for one-dimentional long-sequence linear convolution
R8-core_FPGA_microcontroller
Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis
shapelet_distance_hardware_accelerator
Implementation (VHDL) and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020
vctrop's Repositories
vctrop/image_histogram_data_hiding
Image steganography for data hiding using the histogram-based technique developed by Ni et al., 2006.
vctrop/bank_of_metaheuristics
Implementation of multiple metaheuristics.
vctrop/metaheuristics_for_Laguerre-Volterra_networks_optimization
Optimization of Laguerre-Volterra networks for nonlinear dynamic system identification using diverse metaheuristics
vctrop/article_manager
A toy project to help organizing conference and journal scientific articles
vctrop/shapelet_distance_hardware_accelerator
Implementation (VHDL) and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020
vctrop/AMBA_playground
Design and experimentation with nodes using the AMBA protocol
vctrop/cei_apb3uart
Description of a memory-mapped UART controller using the AMBA 3 APB bus protocol
vctrop/embedded_fall_detection_simulator
Simulates an embedded fall detection system, and its communication with a server
vctrop/embedded_systemsII_coursework
Embedded Systems II discipline - source files
vctrop/laguerre-volterra_network
Implementation of Laguerre-Volterra networks and different methodologies for their optimization, aiming nonlinear dynamic sys. identification
vctrop/overlap_save_convolution
Implementation of the overlap-save algorithm for one-dimentional long-sequence linear convolution
vctrop/R8-core_FPGA_microcontroller
Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis
vctrop/neorv32_victor
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vctrop/semi-supervised_classification