/RISC_32-Bit_Processor_Design

This repository contains a RISC 32-bit processor built on Logisim-evolution.

RISC 32-bit Processor Design

Arnav Kumar Behera, Vedanta Mohapatra

October, 2022

N|Solid

Build Status

In this project, we have implemented a typical RISC-32 Processor having a 5-stage pipeline. The project is built on Logisim-evolution. Kindly refer to Download section in the README.md file of the linked github page for help in installing the software.

Features

  • Implemented a 5-stage RISC 32-bit pipeline, supporting 32-bit intructions and data.
  • Implemented a Register File with 32 registers with each register of size 32 bits.
  • Implemented the memory with 64 locations each of size 32 bits, and the address line of size 6 bits. Each memory location contains either an 32-bit instrucion or a 32-bit data. This can be easily extented to allow for much larger sizes of memory.
  • Intructions supported: MOV, MVI, LOAD, STORE, ADD, ADI, SUB, SUI, AND, ANI, OR, ORI, HLT
  • Support for branched and call instructions might be added in future.

Contents of the Repository

The repository MIPS_32-Bit_Processor_Design contains the following files:

  • Encoding Scheme.pdf: This file contains the basic encoding scheme of our instructions and also contains a dry run of an example program with clear steps.
  • Implementation_Block Level Diagrams.pdf: This file contains the block level implementation of the circuit, and also explains the implementation in great detail.
  • CPU_Design.circ: This file contains the circuit which is built on Logisim-evolution

Softwares used

  • logisim-evolution (Version-3.8.0)
  • LaTeX (Live Version 2022)# RISC 32-bit Processor Design

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