venturezhao

code the world.

@XJTUIAIR-CAG @HuaweiXi'an, China

Pinned Repositories

AIChip_Paper_List
0 1 00
embedded-iot_profile
embedded-iot_profile
0 0 00
Hello_world
My test project
Language:Assembly0 1 40
loongson-gsgpu-dkms-module-mirror
Source code mirror of Loongson GSGPU DKMS module
Language:C0 0 00
MyBlog
MyBlog source files.
Language:HTML0 1 00
oldland-cpu
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Language:Verilog1 1 00
riscv-openocd
RISC-V debug module design reference
Language:C0 1 00
ubuntu_opti
First thing after you installing a pure Ubuntu.
Language:Shell0 2 00
Vscale_plus
A 3-stage in-order single-scalar RISC-V processor
Language:Verilog10 1 03
XJTU-Tripler
XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
Language:VHDL175 14 745

venturezhao's Repositories

venturezhao/oldland-cpu
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Language:Verilog1 1 00
venturezhao/AIChip_Paper_List
0 1 00
venturezhao/embedded-iot_profile
embedded-iot_profile
0 0 00
venturezhao/Hello_world
My test project
Language:Assembly0 1 40
venturezhao/loongson-gsgpu-dkms-module-mirror
Source code mirror of Loongson GSGPU DKMS module
Language:C0 0 00
venturezhao/MyBlog
MyBlog source files.
Language:HTML0 1 00
venturezhao/riscv-openocd
RISC-V debug module design reference
Language:C0 1 00
venturezhao/ubuntu_opti
First thing after you installing a pure Ubuntu.
Language:Shell0 2 00
venturezhao/venturezhao.github.io
My personal cite
Language:HTML1 0